SLLSFW2 September   2023 TUSB211A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Speed EQ
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Speed (LS) Mode
      2. 7.4.2 Full-Speed (FS) Mode
      3. 7.4.3 High-Speed (HS) Mode
      4. 7.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 7.4.5 Shutdown Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High-Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20230821-SS0I-GM2J-SJTF-604LQTWPZBMM-low.svg Figure 5-1 TUSB211A RWB 12-Pin X2QFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO.
EQ 6 I N/A USB High-speed EQ select via external pull down resistor.
Both edge boost and DC boost are controlled by a single pin.
Sampled upon power up. Does not recognize real time adjustments.
Auto selects EQ LEVEL = 3 when left floating.

RESERVED

 11 I 500 kΩ PU Reserved pin for TI test purposes. Leave floating or connect external capacitor to GND for normal operation.
ENA_HS 9 I/O N/A After reset: Output signal ENA_HS. Flag indicating that channel is in High-speed mode. Asserted upon:
1. Detection of USB-IF High-speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 μs – 128 μs].
D2P 7 I/O N/A USB High-speed positive port.
D2M 8 I/O N/A USB High-speed negative port.
GND 10 P N/A Ground
D1M 1 I/O N/A USB High-speed negative port.
D1P 2 I/O N/A USB High-speed positive port.

RESERVED

 3 I/O 500 kΩ PU
1.8 MΩ PD		 Reserved pin for TI test purposes. Leave floating for normal operation.
VCC 12 P N/A Supply power
RSTN 5 I 500 kΩ PU
1.8 MΩ PD		 Device disable/enable.
Low – Device is at reset and in shutdown, and
High - Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven. If the pin is driven, it must be held low until the supply voltage for the device reaches within specifications.
CD 4 O When RSTN asserted there is a 500 kΩ PD After reset: Output CD. Flag indicating that a USB device is attached (connection detected). Asserted from an unconnected state upon detection of DP or DM pull-up resistor. De-asserted upon detection of disconnect.
(1) I = input, O = output, P = power