SNLS757 June   2024 TUSB2E221

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power-Down Mode
      3. 8.4.3  UART Mode
      4. 8.4.4  Auto-Resume ECR
      5. 8.4.5  L2 State Interrupt Modes
      6. 8.4.6  Attach Detect Interrupt Mode
      7. 8.4.7  GPIO Mode
        1. 8.4.7.1 EQ0 as GPIO0
        2. 8.4.7.2 EQ1 as GPIO1
        3. 8.4.7.3 EQ2/INT as GPIO2
      8. 8.4.8  CROSS
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Target Interface
      2. 8.5.2 Register Access Protocol (RAP)
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Dual Port System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 eUSB PHY Settings Recommendation
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Reset
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Example Layout
  11. 10Register Map
    1. 10.1 TUSB2E221 Registers
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Power-Up Reset

The RESETB pin is an active-low reset pin that can also be used as a power-down pin.

The TUSB2E221 does not have power supply sequence requirements between VDD3V3 and VDD1V8.

Make sure the maximum VDD3V3 and VDD1V8 ramp time to reach minimum supply voltages is 2ms.

An internal power-on reset circuit along with the external RESETB input pin allows for proper initialization when RESETB is deasserted high prior to the power rails being valid. If RESETB deasserts high before the power supplies are stable, the internal power-on reset circuit can hold off internal reset until the supplies are stable.

After the RESETB deassertion, followed by internally generated reset signal and 1ms delay, CROSS pin is sampled and latched.

After the RESETB deassertion and after t_RH_READY, the TUSB2E221 is enabled and enters default state, ready to accept eUSB2 packets. Each repeater is either in host repeater mode or device repeater mode depending on the receipt of either host mode enable or peripheral mode enable.