SLLSEN9F May   2015  – March 2022 TUSB320

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Cables, Adapters, and Direct Connect Devices
        1. 7.2.1.1 USB Type-C Receptacles and Plugs
        2. 7.2.1.2 USB Type-C Cables
        3. 7.2.1.3 Legacy Cables and Adapters
        4. 7.2.1.4 Direct Connect Devices
        5. 7.2.1.5 Audio Adapters
    3. 7.3 Feature Description
      1. 7.3.1 Port Role Configuration
        1. 7.3.1.1 Downstream Facing Port (DFP) – Source
        2. 7.3.1.2 Upstream Facing Port (UFP) – Sink
        3. 7.3.1.3 Dual Role Port (DRP)
      2. 7.3.2 Type-C Current Mode
      3. 7.3.3 Accessory Support
        1. 7.3.3.1 Audio Accessory
        2. 7.3.3.2 Debug Accessory
      4. 7.3.4 I2C and GPIO Control
      5. 7.3.5 VBUS Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery Mode
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DRP in I2C Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DFP in I2C Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 UFP in I2C Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-834B63AD-99BD-42E5-B1F2-0C3FC0B091FC-low.gif Figure 5-1 RWB Package,12-Pin X2QFN(Top View)
Table 5-1 Pin Functions
PIN TYPE(3) DESCRIPTION
NAME NO.
CC1 1 I/O Type-C configuration channel signal 1
CC2 2 I/O Type-C configuration channel signal 2
PORT(1) 3 I Tri-level input pin to indicate port mode. The state of this pin is sampled when EN_N is asserted low and VDD is active. This pin is also sampled following a I2C_SOFT_RESET.

H - DFP (Pull-up to VDD if DFP mode is desired)

NC - DRP (Leave unconnected if DRP mode is desired)

L - UFP (Pull-down or tie to GND if UFP mode is desired)
VBUS_DET(1) 4 I 5- to 28-V VBUS input voltage. VBUS detection determines UFP attachment. One 900-kΩ external resistor required between system VBUS and VBUS_DET pin.
ADDR(1) 5 I Tri-level input pin to indicate I2C address or GPIO mode:

H - I2C is enabled and I2C 7-bit address is 0x61.

NC - GPIO mode (I2C is disabled)

L - I2C is enabled and I2C 7-bit address is 0x60.

ADDR pin should be pulled up to VDD if high configuration is desired
INT_N/OUT3(1) 6 O The INT_N/OUT3 is a dual-function pin. When used as the INT_N, the pin is an open drain output in I2C control mode and is an active low interrupt signal for indicating changes in I2C registers. When used as OUT3, the pin is in audio accessory detect in GPIO mode: no detection (H), audio accessory connection detected (L).
SDA/OUT1(1)(2) 7 I/O The SDA/OUT1 is a dual-function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the TUSB320 device is in UFP mode: Refer to Table 7-3 for more details.
SCL/OUT2(1)(2) 8 I/O The SCL/OUT2 is a dual function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the TUSB320 device is in UFP mode: Refer to Table 7-3 for more details.
ID(1) 9 O Open drain output; asserted low when the CC pins detect device attachment when port is a source (DFP), or dual-role (DRP) acting as source (DFP).
GND 10 G Ground
EN_N 11 I Enable signal; active low. Pulled up to VDD internally to disable the TUSB320 device. If controlled externally, must be held high at least for 50 ms after VDD has reached its valid voltage level.
VDD 12 P Positive supply voltage. VDD must ramp within 25 ms or less
(1) When VDD is off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, ID, OUT[3:1] pins) could back-drive the TUSB320 device if not handled properly. When necessary to pull these pins up, it is recommended to pullup PORT, ADDR, INT_N/OUT3, and ID to the device VDD supply. The VBUS_DET must be pulled up to VBUS through a 900-kΩ resistor.
(2) When using the 3.3 V supply for I2C, the end user must ensure that the VDD is 3 V and above. Otherwise the I2C may back power the device.
(3) I = input, O = output, P = power