SLLSEI0E July   2015  – July 2024 TUSB4020BI

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings #GUID-E9510BAC-794F-43CD-A047-0D0FFB7C50BE/ABSMAXNOTE
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 3.3V I/O Electrical Characteristics
    6. 5.6 Hub Input Supply Current
    7. 5.7 Power-Up Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 External Configuration Interface
    5. 6.5 Programming
      1. 6.5.1 One-Time Programmable (OTP) Configuration
      2. 6.5.2 I2C EEPROM Operation
      3. 6.5.3 SMBus Target Operation
    6. 6.6 Register Maps
      1. 6.6.1 Configuration Registers
        1. 6.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 6.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 6.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 6.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 6.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 6.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 6.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 6.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 6.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 6.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 6.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 6.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 6.6.1.13 Language ID LSB Register (offset = 20h)
        14. 6.6.1.14 Language ID MSB Register (offset = 21h)
        15. 6.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 6.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 6.6.1.17 Product String Length Register (offset = 24h)
        18. 6.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 6.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 6.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 6.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 6.6.1.22 Charging Port Control Register (offset = F2h)
        23. 6.6.1.23 Device Status and Command Register (offset = F8h)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Crystal Requirements
      2. 7.1.2 Input Clock Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Upstream Port Implementation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Downstream Port 1 Implementation
      3. 7.2.3 Downstream Port 2 Implementation
      4. 7.2.4 VBUS Power Switch Implementation
      5. 7.2.5 Clock, Reset, and Miscellaneous
      6. 7.2.6 Power Implementation
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply
      2. 7.3.2 Downstream Port Power
      3. 7.3.3 Ground
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Placement
        2. 7.4.1.2 Package Specific
        3. 7.4.1.3 Differential Pairs
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision D (January 2022) to Revision E (July 2024)

  • Updated the data sheet to include inclusive terminologyGo
  • Added the XO pin to the Absolute Maximum Ratings voltage parametersGo
  • Changed the minimum voltage for the XI pin from: –0.3V to: –0.4VGo
  • Added maximum junction temperature to the Absolute Maximum Ratings tableGo
  • Added the XI, XO voltage to the Recommended Operating Conditions table Go

Changes from Revision C (April 2018) to Revision D (January 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Removed 1M feedback resistor requirement for crystal on pages 4, 11, 12, and 31Go
  • Updated the pin description from: SMBus target address bits 2 and 3 are always 1 for TUSB4020BI to: SMBus target address bit 3 is always 1 for TUSB4020BI Go
  • Corrected the default register setting for the Register offset 9h Go
  • Updated the Clock, Reset, and Miscellaneous Schematic in the Clock, Reset, and Miscellaneous sectionGo

Changes from Revision B (June 2017) to Revision C (April 2018)

  • Changed the Absolute Maximum Ratings table, added pin voltagesGo

Changes from Revision A (March 2016) to Revision B (June 2017)

  • Added SMBUS Programming current to the Hub Input Supply Current table Go
  • Added Note to the SMBus Target Operation sectionGo

Changes from Revision * (July 2015) to Revision A (March 2016)