SLLSEI0E July   2015  – July 2024 TUSB4020BI

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings #GUID-E9510BAC-794F-43CD-A047-0D0FFB7C50BE/ABSMAXNOTE
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 3.3V I/O Electrical Characteristics
    6. 5.6 Hub Input Supply Current
    7. 5.7 Power-Up Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 External Configuration Interface
    5. 6.5 Programming
      1. 6.5.1 One-Time Programmable (OTP) Configuration
      2. 6.5.2 I2C EEPROM Operation
      3. 6.5.3 SMBus Target Operation
    6. 6.6 Register Maps
      1. 6.6.1 Configuration Registers
        1. 6.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 6.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 6.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 6.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 6.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 6.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 6.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 6.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 6.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 6.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 6.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 6.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 6.6.1.13 Language ID LSB Register (offset = 20h)
        14. 6.6.1.14 Language ID MSB Register (offset = 21h)
        15. 6.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 6.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 6.6.1.17 Product String Length Register (offset = 24h)
        18. 6.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 6.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 6.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 6.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 6.6.1.22 Charging Port Control Register (offset = F2h)
        23. 6.6.1.23 Device Status and Command Register (offset = F8h)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Crystal Requirements
      2. 7.1.2 Input Clock Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Upstream Port Implementation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Downstream Port 1 Implementation
      3. 7.2.3 Downstream Port 2 Implementation
      4. 7.2.4 VBUS Power Switch Implementation
      5. 7.2.5 Clock, Reset, and Miscellaneous
      6. 7.2.6 Power Implementation
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply
      2. 7.3.2 Downstream Port Power
      3. 7.3.3 Ground
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Placement
        2. 7.4.1.2 Package Specific
        3. 7.4.1.3 Differential Pairs
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TUSB4020BI PHP Package,48-Pin HTQFP(Top View)Figure 4-1 PHP Package,48-Pin HTQFP(Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
CLOCK AND RESET SIGNALS
GRSTz11I
PU		Global power reset. This reset brings all of the TUSB4020BI internal registers back to the default state. When GRSTz is asserted, the device is completely nonfunctional.
XI38ICrystal input. This terminal is the crystal input for the internal oscillator. The input can alternately be driven by the output of an external oscillator.
XO39OCrystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin can be left unconnected.
USB UPSTREAM SIGNALS
USB_DP_UP26I/OUSB high-speed differential transceiver (positive)
USB_DM_UP27I/OUSB high-speed differential transceiver (negative)
USB_R124IPrecision resistor reference. Connect a 9.53kΩ ±1% resistor between USB_R1 and GND.
USB_VBUS9IUSB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9kΩ ±1% resistor and to ground through a 10kΩ ±1% resistor from the signal to ground.
USB DOWNSTREAM SIGNALS
USB_DP_DN141I/OUSB high-speed differential transceiver (positive) downstream port 1.
USB_DM_DN142I/OUSB high-speed differential transceiver (negative) downstream port 1.
PWRCTL1/BATEN14I/O
PD		USB port 1 power-on control for downstream power or battery charging enable. The terminal is used for control of the downstream power switch for Port 1.
In addition, the value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register.
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR1z5I
PU		USB DS port 1 overcurrent detection input. This terminal is used to connect the overcurrent output of the downstream port power switch for port 1.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
If power management is enabled, review the power switch to determine the required external circuitry. In ganged mode, either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent is reported as a hub event instead of a port event.
USB_DP_DN214I/OUSB high-speed differential transceiver (positive) downstream port 2.
USB_DM_DN215I/OUSB high-speed differential transceiver (negative) downstream port 2.
PWRCTL2/BATEN26I/O
PD		Power-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power switch for port 2.
The value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for port 2 as indicated in the Battery Charging Support register.
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR2z8I
PU		Overcurrent detection for downstream port 2. This terminal is used to connect the over current output of the downstream port power switch for port 2.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
If power management is enabled, review the power switch to determine the required external circuitry. In ganged mode either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent is reported as a hub event instead of a port event.
I2C/SMBUS SIGNALS
SCL/SMBCLK2I/O
PD		I2C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input.
When SMBUSz = 1, this terminal acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus host.
This pin must be pulled up to use the OTP ROM.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT3I/O
PD		I2C data/SMBus data. Function of terminal depends on the setting of the SMBUSz input.
When SMBUSz = 1, this terminal acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host.
This pin must be pulled up to use the OTP ROM.
Can be left unconnected if external interface not implemented.
TEST AND MISCELLANEOUS SIGNALS
SMBUSz22I
PU		SMBUS mode.
The value of the terminal is sampled at the deassertion of reset to enable I2C or SMBus mode.
0 = SMBus mode selected
1 = I2C mode selected
After reset, this signal is driven low by the TUSB4020BI. Due to this behavior, TI recommends to not tie directly to supply but instead pull up or pull down using external resistor.
PWRCTL_POL21I/O
PD		Power control polarity.
The value of the terminal is sampled at the deassertion of reset to set the polarity of PWRCTL[2:1].
0 = PWRCTL polarity is active high.
1 = PWRCTL polarity is active low.
After reset, this signal is driven low by the TUSB4020BI. Due to this behavior, TI recommends to not tie directly to supply but instead pull up or pull down using external resistor.
GANGED/SMBA2/
HS_UP		35I
PU		Ganged operation enable/SMBus address bit 2/ high-speed status for upstream port
The value of the terminal is sampled at the deassertion of reset to set the power switch and over current detection mode as follows:
0 = Individual power control supported when power switching is enabled.
1 = Power control gangs supported when power switching is enabled.
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus target address bit 2. SMBus target address bit 3 is always 1 for the TUSB4020BI.
After reset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a high-speed USB capable port.
Note: individual power control must be enabled for battery charging applications.
FULLPWRMGMTz/
SMBA1		36I, PUFull power management enable/ SMBus Address bit 1.
The value of the terminal is sampled at the deassertion of reset to set the power switch control follows:
0 = Power switching supported
1 = Power switching not supported
Full power management is the ability to control power to the downstream ports of the TUSB4020BI using PWRCTL[2:1]/BATEN[2:1].
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus target address bit 1. SMBus target address bit 3 is always 1 for the TUSB4020BI.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal is driven low by the TUSB4020BI. Due to this behavior, TI recommends to not tie directly to supply but instead pull up or pull down using external resistor.
Note: power switching must be supported for battery charging applications.
RSVD16, 17, 19, 20, 28, 29, 31, 32, 43, 44, 46, 47I/OReserved. These pins are for internal use only and must be left unconnected on PCB.
TEST10I
PD		TEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is reserved for factory use. TI recommends to pull down this terminal to ground.
POWER AND GROUND SIGNALS
VDD1, 12, 18, 30, 34, 45PWR1.1V power rail
VDD337, 13, 23, 25, 33, 37, 40, 48PWR3.3V power rail
GNDPAD—Ground
(1) I = input, O = output, I/O = input/output, PU = internal pullup resistor, PD = internal pulldown resistor, and PWR = power signal