SLDS251A December   2019  – May 2022 TUSS4470

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Direct Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transducer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 REG_USER Registers

Table 7-5 lists the REG_USER registers. All register offset addresses not listed in Table 7-5 should be considered as reserved locations and the register contents should not be modified.

Table 7-5 REG_USER Registers
AddressAcronymRegister NameSection
0x10BPF_CONFIG_1Bandpass filter settingsGo
0x11BPF_CONFIG_2Bandpass filter settingsGo
0x12DEV_CTRL_1Log-amp configurationGo
0x13DEV_CTRL_2Log-amp configurationGo
0x14DEV_CTRL_3Device ConfigurationGo
0x16VDRV_CTRLVDRV Regulator ControlGo
0x17ECHO_INT_CONFIGEcho Interrupt ControlGo
0x18ZC_CONFIGZero Crossing configurationGo
0x1ABURST_PULSEBurst pulse configurationGo
0x1BTOF_CONFIGTime of Flight ConfigGo
0x1CDEV_STATFault status bitsGo
0x1DDEVICE_IDDevice IDGo
0x1EREV_IDRevision IDGo

Complex bit access types are encoded to fit into small table cells. Table 7-6 shows the codes that are used for access types in this section.

Table 7-6 REG_USER Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 BPF_CONFIG_1 Register (Address = 0x10) [reset = 0x0]

BPF_CONFIG_1 is shown in Table 7-7.

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Table 7-7 BPF_CONFIG_1 Register Field Descriptions
BitFieldTypeResetDescription
7BPF_FC_TRIM_FRCR/W0x0Override factor settings for Bandpass filter trim and control via BPF_FC_TRIM register. Valid only when BPF_BYPASS = 0

0x0 = Factory trim

0x1 = Override Factory trim

6BPF_BYPASSR/W0x0Select between Bandpass filter or high pass filter

0x0 = BPF Enabled

0x1 = HPF Enabled (BPF Bypass)

5:0BPF_HPF_FREQR/W0x0If BPF_BYPASS = 0:
Band pass filter center frequency. See "Bandpass filter center frequency configuration" table
If BPF_BYPASS = 1:
High pass filter corner frequency
0x00 - 0x0F - 200kHz
0x10 - 0x1F - 400kHz
0x20 - 0x2F - 50kHz
0x30 - 0x3F - 100kHz

7.6.1.2 BPF_CONFIG_2 Register (Address = 0x11) [reset = 0x0]

BPF_CONFIG_2 is shown in Table 7-8.

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Table 7-8 BPF_CONFIG_2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0Reserved
5:4BPF_Q_SELR/W0x0Bandpass filter Q factor. Valid only when BPF_BYPASS = 0

0x0 = 4

0x1 = 5

0x2 = 2

0x3 = 3

3:0BPF_FC_TRIMR/W0x0Offset BPF_HPF_FREQ when BPF_FC_TRIM_FRC = 1:
BPF_HPF_FREQ = BPF_HPF_FREQ + BPF_FC_TRIM
See "Bandpass filter center frequency range extension" table.

7.6.1.3 DEV_CTRL_1 Register (Address = 0x12) [reset = 0x0]

DEV_CTRL_1 is shown in Table 7-9.

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Table 7-9 DEV_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7LOGAMP_FRCR/W0x0Override for factory settings for LOGAMP_SLOPE_ADJ and LOGAMP_INT_ADJ
6:4LOGAMP_SLOPE_ADJR/W0x0Slope or gain adjustment at the final output on VOUT pin. Slope adjustment depends on the setting of VOUT_SCALE_SEL.

0x0 = 3.0× VOUT_SCALE_SEL+4.56×VOUT_SCALE_SEL V/V

0x1 = 3.1× VOUT_SCALE_SEL+4.71×VOUT_SCALE_SEL V/V

0x2 = 3.2× VOUT_SCALE_SEL+4.86×VOUT_SCALE_SEL V/V

0x3 = 3.3× VOUT_SCALE_SEL+5.01×VOUT_SCALE_SEL V/V

0x4 = 2.6× VOUT_SCALE_SEL+3.94×VOUT_SCALE_SEL V/V

0x5 = 2.7× VOUT_SCALE_SEL+ 4.10×VOUT_SCALE_SEL V/V

0x6 = 2.8× VOUT_SCALE_SEL+4.25×VOUT_SCALE_SEL V/V

0x7 = 2.9× VOUT_SCALE_SEL+4.4×VOUT_SCALE_SEL V/V

3:0LOGAMP_INT_ADJR/W0x0Logamp Intercept adjustment. See "Logamp intercept adjustment" table in specification for values.

7.6.1.4 DEV_CTRL_2 Register (Address = 0x13) [reset = 0x0]

DEV_CTRL_2 is shown in Table 7-10.

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Table 7-10 DEV_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7LOGAMP_DIS_FIRSTR/W0x0Disable first logamp stage to reduce quiescent current
6LOGAMP_DIS_LASTR/W0x0Disable last logamp stage quiescent current
3RESERVEDR0x0Reserved
2VOUT_SCALE_SELR/W0x0Select VOUT scaling

0x0 = Select Vout gain to map output to 3.3 V

0x1 = Select Vout gain to map output to 5.0 V

1:0LNA_GAINR/W0x0Adjust LNA Gain in V/V

0x0 = 15 V/V

0x1 = 10 V/V

0x2 = 20 V/V

0x3 = 12.5 V/V

7.6.1.5 DEV_CTRL_3 Register (Address = 0x14) [reset = 0x0]

DEV_CTRL_3 is shown in Table 7-11.

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Table 7-11 DEV_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
4:2DRV_PLS_FLT_DTR/W0x0Driver Pulse Fault Deglitch Time.
In IO_MODE = 0 or IO_MODE = 1, DRV_PULSE_FLT will be set if start of burst is triggered and IO2 pin has not toggled for greater than deglitch Time.
In IO_MODE = 2, DRV_PULSE_FLT will be set if start of burst is triggered and if IO1 or IO2 do not toggle a period longer than the deglitch time except when both pins are high.

0x0 = 64 µs

0x1 = 48 µs

0x2 = 32 µs

0x3 = 24 µs

0x4 = 16 µs

0x5 = 8 µs

0x6 = 4 µs

0x7 = Check Disabled

1:0IO_MODER/W0x0Configuration for low voltage IO pins.

0x0 = IOMODE 0

0x1 = IOMODE 1

0x2 = IOMODE 2

0x3 = IOMODE 3

7.6.1.6 VDRV_CTRL Register (Address = 0x16) [reset = 0x20]

VDRV_CTRL is shown in Table 7-12.

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Table 7-12 VDRV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6DIS_VDRV_REG_LSTNR/W0x0Automatically disable VDRV charging in listen mode every time after burst mode is exited given VDRV_TRIGGER =0x0.

0x0 = Do not automatically disable VDRV charging

0x1 = Automatically disable VDRV charging

5VDRV_HI_ZR/W0x1Turn off current source between VPWR and VRDV and disable VDRV regulation.

0x0 = VDRV not Hi-Z

0x1 = VDRV in Hi-Z mode

4VDRV_CURRENT_LEVELR/W0x0Pull up current at VDRV pin

0x0 = 10 mA

0x1 = 20 mA

3:0VDRV_VOLTAGE_LEVELR/W0x0Regulated Voltage at VDRV pin Value is calculated as :
VDRV = VDRV_VOLTAGE_LEVEL + 5 [V]

7.6.1.7 ECHO_INT_CONFIG Register (Address = 0x17) [reset = 0x7]

ECHO_INT_CONFIG is shown in Table 7-13.

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Table 7-13 ECHO_INT_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0Reserved
4ECHO_INT_CMP_ENR/W0x0Enable echo interrupt comparator output
3:0ECHO_INT_THR_SELR/W0x7Threshold level to issue interrupt on OUT4 pin. Applied to Low pass filter output.
If VOUT_SCALE_SEL=0x0 :
Threshold = 0.04 x ECHO_INT_THR_SEL + 0.4 [V]
If VOUT_SCALE_SEL=0x1:
Threshold = 0.06 x ECHO_INT_THR_SEL + 0.6 [V]

7.6.1.8 ZC_CONFIG Register (Address = 0x18) [reset = 0x14]

ZC_CONFIG is shown in Table 7-14.

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Table 7-14 ZC_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7ZC_CMP_ENR/W0x0Enable Zero Cross Comparator for Frequency detection
6ZC_EN_ECHO_INTR/W0x0When set, provides ZC information only when object is detected
5ZC_CMP_IN_SELR/W0x0Zero Comparator Input Select

0x0 = INP - VCM

0x1 = INP - INN

4:3ZC_CMP_STG_SELR/W0x2Zero Cross Comparator Stage Select
2:0ZC_CMP_HYSTR/W0x4Zero Cross Comparator Hysteresis Selection

0x0 = 30 mV

0x1 = 80 mV

0x2 = 130 mV

0x3 = 180 mV

0x4 = 230 mV

0x5 = 280 mV

0x6 = 330 mV

0x7 = 380 mV

7.6.1.9 BURST_PULSE Register (Address = 0x1A) [reset = 0x0]

BURST_PULSE is shown in Table 7-15.

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Table 7-15 BURST_PULSE Register Field Descriptions
BitFieldTypeResetDescription
7HALF_BRG_MODER/W0x0Use output driver in half-bridge mode.
When enabled, drive both high-side FET together and low-side FETs together.

0x0 = Disable half-bridge mode

0x1 = Enable half bridge mode

6PRE_DRIVER_MODER/W0x0Pre-driver mode to drive external FETs

0x0 = Disable pre-driver mode

0x1 = Enable pre-driver mode

5:0BURST_PULSER/W0x0Number of burst pulses. REG_VALUE=0x00 enables continuous burst mode

7.6.1.10 TOF_CONFIG Register (Address = 0x1B) [reset = 0x0]

TOF_CONFIG is shown in Table 7-16.

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Table 7-16 TOF_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7SLEEP_MODE_ENR/W0x0For entering or exiting sleep mode

0x0 = Wake up or exit Sleep Mode

0x1 = Enter sleep mode

6STDBY_MODE_ENR/W0x0For entering or exiting standby mode

0x0 = Exit Standby Mode

0x1 = Enter Standby mode

5:2RESERVEDR0x0Reserved
1VDRV_TRIGGERR/W0x0Control charging of VDRV pin when DIS_VDRV_REG_LSTN = 1. This has no effect when VDRV_HI_Z=0x1.

0x0 = Disable IVDRV

0x1 = Enable IVDRV

0CMD_TRIGGERR/W0x0For IO_MODE=0x0, control enabling of burst mode. Ignored for other IO_MODE values.

0x0 = Disable burst mode

0x1 = Enable burst mode

7.6.1.11 DEV_STAT Register (Address = 0x1C) [reset = 0x0]

DEV_STAT is shown in Table 7-17.

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Table 7-17 DEV_STAT Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0Reserved
3VDRV_READYR0x0VDRV pin voltage status

0x0 = VDRV is below configured voltage

0x1 = VDRV is equal or above configured voltage

2PULSE_NUM_FLTR0x0The Driver has not received the number of pulses defined by BURST_PULSE
1DRV_PULSE_FLTR0x0The Driver has been stuck in a single state in burst mode for a period longer than delgitch time set by DRV_PLS_FLT_DT
0EE_CRC_FLTR0x0CRC error for internal memory

7.6.1.12 DEVICE_ID Register (Address = 0x1D) [reset = X]

DEVICE_ID is shown in Table 7-18.

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Table 7-18 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_IDRXDevice ID: 0xB9

7.6.1.13 REV_ID Register (Address = 0x1E) [reset = 0x2]

REV_ID is shown in Table 7-19.

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Table 7-19 REV_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0REV_IDR0x2Revision ID