SLUSDD5A April   2019  – December 2020 UC1825B-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Methods
      2. 7.3.2 Synchronization
      3. 7.3.3 High Current Outputs
      4. 7.3.4 Open Loop Test Circuit
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Design Theory
        1. 8.2.1.1 Switching Frequency
        2. 8.2.1.2 Transformer
        3. 8.2.1.3 RCD and Diode Clamp
        4. 8.2.1.4 Output Diode
        5. 8.2.1.5 Main Switching MOSFETs
        6. 8.2.1.6 Output Filter and Capacitance
        7. 8.2.1.7 Compensation
        8. 8.2.1.8 Sense Resistor
    3. 8.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
      5. 10.1.5 Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.7 Compensation

Type IIB compensation was picked for the topology, adding a pole and a zero to the frequency response. The location of where the pole and zero should be placed will depend on the desired crossover frequency and the ESR zero of the output capacitors. The zero in compensation should be placed at least a decade before the crossover frequency for the maximum phase boost. Note that compensation values were picked with a crossover frequency of 5 kHz in mind for this design. The pole from the compensation should be placed at the zero created by the ESR of the output capacitor.

Equation 49. fzESR= 12π×Cout×ESR=12π×1146 μF×0.009 Ω=15.43 kHz
Equation 50. fpCOMP=12π×RCOMP×CHF=12π×4.75 kΩ×2200 pF=15.23 kHz
Equation 51. fzCOMP=12π×RCOMP×CCOMP=12π×4.75 kΩ×0.12 μF=279 Hz

The zero from compensation was placed well before the 500-Hz mark which is appropriate. The pole from compensation was optimized while the circuit was tested and thus it was found that placing the pole a little bit earlier smoothed out the frequency response.