SLUS336A June   1998  – December 2016 UC1854 , UC2854 , UC3854

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Protection Inputs
        2. 9.2.2.2 Control Inputs
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Figure 12 and Figure 13 show good layout practice. The timing capacitor (C1) and bypass capacitors for VCC and VREF (C3 and C5) must be connected directly from their respective pins to GND through the shortest route. Ensure that the ISEN and MULTOUT pins do not drop more than 0.5 V below the GND pin; accomplished by connecting a Schottky diode (D6) between GND and MULTOUT pins. The local controller GND must be connected to the power circuit at a single point between the source of the power MOSFET and the current sense resistor (R14). The power trace running between the power MOSFET source and current sense resistor (R14) must be kept short. Traces from the upper terminals of R9 and R10 must run directly to each side of the current sense resistor and not be shared with any other signal.

To minimize the possiblity of interference caused by magnetic coupling from the boost inductor, the device must be located at least 1 in. away from the boost inductor. TI recommends the device not be placed underneath magnetic elements.

11.2 Layout Example

UC1854 UC2854 UC3854 SLUS336_UC1854_2854_3854_FRONTVIEW.gif Figure 12. Layout Diagram (Top View)
UC1854 UC2854 UC3854 SLUS336_UC1854_2854_3854_BOTTOMVIEW.gif Figure 13. Layout Diagram (Bottom View)