SLUSDO2D June   2020  – August 2024 UCC21540-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Programmable Dead Time
    6. 7.6 Power-Up UVLO Delay to OUTPUT
    7. 7.7 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in the UCC21540-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCCI
        2. 8.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select Dead Time Resistor and Capacitor
        3. 9.2.2.3 Select External Bootstrap Diode and Its Series Resistor
        4. 9.2.2.4 Gate Driver Output Resistor
        5. 9.2.2.5 Gate to Source Resistor Selection
        6. 9.2.2.6 Estimating Gate Driver Power Loss
        7. 9.2.2.7 Estimating Junction Temperature
        8. 9.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.8.1 Selecting a VCCI Capacitor
          2. 9.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.8.3 Select a VDDB Capacitor
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.13 Revision History

Changes from Revision C (February 2021) to Revision D (August 2024)

  • Deleted HBM and CDM ESD classification levels from FeaturesGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Changed propagation delay from 40ns max to 33ns typicalGo
  • Deleted bullet on 5-ns maximum delay matchingGo
  • Changed maximum pulse width distortion from 5.5ns to 6nsGo
  • Changed 35us maximum VDD power up delay to 10us maximumGo
  • Deleted bullets on certifications, certifications ongoingGo
  • Changed minimum 100V/ns CMTI to 125V/nsGo
  • Deleted sentence on rejecting input transients shorter than 5nsGo
  • Changed negative voltage handling from -2V for 200ns to -5V for 50ns for input pinsGo
  • Changed schematic DT capacitor size from >=2.2nF to <=1nFGo
  • Changed recommended DT pin condition and capacitor size on DT pinGo
  • Changed VCCI absmax from 6V to 20VGo
  • Changed VDDA-VSSA and VDDB-VSSB absmax from 20V to 30VGo
  • Changing all -0.5V minimum to -0.3V to keep consistent with newly released datasheetsGo
  • Changing all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly released datasheetsGo
  • Changed input signal voltage transient test condition to 50ns and absolute minimum to -5VGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Changed VCCI recommended max from 5.5V to 18VGo
  • Changed VDDA-VSSA and VDDB-VSSB recommended max from 18V to 25VGo
  • Changed 5V-UVLO recommended minimum VDDA/B voltage from 6V to 6.5VGo
  • Deleted ambient temperature specGo
  • Updated values from RθJA = 69.7°C/W, RθJC(top) = 33.1°C/W, RθJB = 29.0°C/W, ψJT = 20.0°C/W, ψJB = 28.3°C/W to RθJA = 74.1°C/W, RθJC(top) = 34.1°C/W, RθJB = 32.8°C/W, ψJT = 23.7°C/W, ψJB = 32.1°C/WGo
  • Updated values from PD = 915mW, PDI = 15mW, PDA/PDB = 450mW to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW. Go
  • Added VIMP = 7692Vpk and changed Viosm from 8000V to 10000V per latest insulation standardGo
  • Deleted safety related certifications sectionGo
  • Updated values from IS = 73mA, PS = 15mW/880mW/880mW/1775mW to IS = 66mA, PS = 50mW/800mW/800mW/1650mW Go
  • Changed test condition from VDDA=VDDB=12V to VDDA=VDDB=15VGo
  • Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mAGo
  • Updated IVCCI operating current Typ value from 2.5mA to 3.0mA and added Max value 3.5mAGo
  • Added IVDDA/IVDDB operating current Max = 4.2mAGo
  • Updated values from Rising threshold Min = 5.0V, Typ = 5.5V, Max = 5.9V to Min = 5.7V, Typ = 6.0V, Max = 6.3V Go
  • Updated values from Falling threshold Min = 4.7V, Typ = 5.2V, Max = 5.6V to Min = 5.4V, Typ = 5.7V, Max = 6.0V Go
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max = 8.9V Go
  • Updated values from Rising threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max = 8.4V Go
  • Updated Input high threshold Min value from 1.6V to 1.2VGo
  • Updated Input low threshold Max value from 1.25V to 1.2VGo
  • Deleted peak current minimum valuesGo
  • Deleted output resistance maximum valuesGo
  • Deleted output voltage at high state minimum. Changed typical value from 11.95V to 14.95V. Changed test condition from VDD=12V to VDD=15V. Go
  • Deleted output voltage at low state maximum. Changed test condition from VDD=12V to VDD=15V. Go
  • Changed driver active pull down typical value from 1.75V to 1.6V and max value from 2.1V to 2V.Go
  • Deleted dead time matching rowsGo
  • Changed test condition from VDDA=VDDB=12V to VDDA=VDDB=15VGo
  • Deleted minimum pulse width typical valueGo
  • Changed propagation delay TPDHL and TPDLH from Typ=28ns, Max = 40ns to Min = 26ns, Typ = 33ns, Max = 45nsGo
  • Changed pulse width distortion max from 5.5ns to 6nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Deleted VCCI power up delay typical 40us and changed max from 59us to 50usGo
  • Deleted VDD power up delay typical 23us and changed max from 35us to 10usGo
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated thermal curves to match updated characteristicsGo
  • Updated typical char plots to show device characteristics Go
  • Deleted language on deglitch filter. Changed minimum pulse width from 10ns typical to 20ns maximum. Go
  • Changed recommended decoupling capacitor placement from 2.2nF or greater to ≤1nFGo
  • Changed UVLO delay timingGo
  • Updated functional block diagramGo
  • Changed clamping voltage typical value from 1.75V to 1.6VGo
  • Changed DIS pull-down resistor size from 50kOhm to 200kOhmGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated ESD diode structureGo
  • Deleted incomplete sentence due to datasheet draft errorGo
  • Changed DT capacitor recommendation from >=2.2nF to <=1nF Go
  • Deleted sentence on DT pin steady state voltage Go
  • Changed DT capacitor size in application schematic Go
  • Changed DT capacitor size from 2.2nF to <=1nFGo
  • Changed DT capacitor recommendation from >=2.2nF to <=1nFGo

Changes from Revision B (February 2021) to Revision C (February 2021)

  • Updated Reinforced Isolation Capcitor Life Time Projection Figure Go

Changes from Revision A (July 2020) to Revision B (February 2021)

  • Added functional safety quality-managed to features listGo
  • Changed Features, Applications, and Description sectionsGo
  • Added initial release of UCC21540A-Q1 device.Go
  • Added UCC21540A-Q1 UVLO thresholds Go
  • Added UCC21540A-Q1 UVLO threshold plotsGo

Changes from Revision * (May 2020) to Revision A (July 2020)

  • Changed marketing status from Advance Information to initial release. Go