SLUSEU6D May   2023  – August 2024 UCC21550-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21550-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Switching Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitance from VCCI to GND, VVDDx = 12V (for 5V and 8V UVLO) or 15V (for 12V UVLO) , 1.1-µF capacitance from VDDA and VDDB to VSSA and VSSB, DT pin floating, EN = VCC or DIS = GND, TJ = –40°C to +150°C,  CL = 0 pF, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRISE Output Rise Time CL=1.8nF, VDDx=12V, 20% to 80% 8 ns
CL=1.8nF, VDDx=25V, 20% to 80% 8
tFALL Output Fall Time CL=1.8nF, VDDx=12V, 10% to 90% 8 ns
CL=1.8nF, VDDx=25V, 10% to 90% 8
tPDLH Propagation Delay – Low to High Input Pulse Width = 100ns, 500kHz, measure with Input VIH to output 10%  26 33 45 ns
tPDHL Propagation Delay – High to Low Input Pulse Width = 100ns, 500kHz, measure with Input VIL to output 90% 26 33 45 ns
tPD_DIS_HL DIS Response Delay – High to Low
tEN/DIS_FIL = 20 ns (typ), VDD=VDD_ON+0.2V and above,
Input Pulse Width = 100ns, 500kHz 		27 48 80 ns
tPD_DIS_LH DIS Response Delay – Low to High 27 48 80 ns
tPWmin Minimum Input Pulse Width That Passes to Output VDD=VDD_ON+0.2V and above  4 12 30 ns
tDM Propagation Delay Matching for Dual Channel Driver Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 0 6.5 ns
Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 0 5 ns
tPWD Pulse Width Distortion Input Pulse Width = 100ns, 500kHz
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|		 0 5 ns
|CMH| High-level Common Mode Transient Immunity VCM = 1500V 125 V/ns
|CML| Low-level Common Mode Transient Immunity 125 V/ns