SLUSET9H December   2022  – October 2024 UCC21551-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Enable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21551x-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
  • DW|16
  • DFJ|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Revision History

Changes from Revision G (June 2024) to Revision H (October 2024)

  • Added CH-to-CH creepage: >5.3mm in DFJ and >3.3mm in DWKGo
  • Added 12-V and 17-V UVLO DFJ28 package variants Go
  • Added >5.3mm creepage comment for DFJ28 packageGo
  • Added DFJ28 package pin configurationsGo
  • Added DFJ package in isolation voltage specGo
  • Added DFJ package thermal information Go
  • Added >8.3mm creepage for DFJ packageGo
  • Added safety limiting values for DFJ packageGo
  • Added thermal derating limiting current and limiting power curves for DFJ packageGo

Changes from Revision F (May 2024) to Revision G (June 2024)

  • Deleted "5ns maximum delay matching" bulletGo
  • Changed maximum pulse-width distortion bullet from 6ns to 5nsGo
  • Updated overvoltage category for <600VRMS from I-IV to I-IIIGo
  • Updated overvoltage category for <1000VRMS from I-III to I-IIGo
  • Added safety limiting values for DW packageGo
  • Added thermal derating limiting current and limiting power curves for DW packageGo
  • Changed section to callout EN pin and not DIS pinGo

Changes from Revision E (January 2024) to Revision F (May 2024)

  • Added A and B DWK package versions Production DataGo
  • Added A DW package version Production DataGo
  • Added capacitance limitation on DT pin descriptionGo
  • Updated ESD spec to match industry standardsGo
  • Updated VCC quiscent current spec to have tighter toleranceGo
  • Updated VDDx quiscent current spec to have tighter toleranceGo

Changes from Revision D (September 2023) to Revision E (January 2024)

  • Changed D version from Advance Information to Production DataGo

Changes from Revision C (August 2023) to Revision D (September 2023)

  • Added junction temperature range to the Switching CharacteristicsGo

Changes from Revision B (June 2023) to Revision C (August 2023)

  • Added Functional Safety Capable bullets to FeaturesGo

Changes from Revision A (May 2023) to Revision B (June 2023)

  • Changed C version from Advance Information to Production DataGo
  • Changed D version from Product Preview to Advance InformationGo

Changes from Revision * (December 2022) to Revision A (May 2023)

  • Added D version with 17-V UVLOGo
  • Changed DT formula in Dead Time Setting GuidelinesGo