SLUSET9G
December 2022 – June 2024
UCC21551-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings (Automotive)
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Power Ratings
5.6
Insulation Specifications
5.7
Safety Limiting Values
5.8
Electrical Characteristics
5.9
Switching Characteristics
5.10
Insulation Characteristics Curves
5.11
Typical Characteristics
6
Parameter Measurement Information
6.1
Propagation Delay and Pulse Width Distortion
6.2
Rising and Falling Time
6.3
Input and Enable Response Time
6.4
Programmable Dead Time
6.5
Power-up UVLO Delay to OUTPUT
6.6
CMTI Testing
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VDD, VCCI, and Undervoltage Lock Out (UVLO)
7.3.2
Input and Output Logic Table
7.3.3
Input Stage
7.3.4
Output Stage
7.3.5
Diode Structure in the UCC21551x-Q1
7.4
Device Functional Modes
7.4.1
Enable Pin
7.4.2
Programmable Dead-Time (DT) Pin
7.4.2.1
Tying the DT Pin to VCC
7.4.2.2
DT Pin Connected to a Programming Resistor Between DT and GND Pins
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Designing INA/INB Input Filter
8.2.2.2
Select External Bootstrap Diode and its Series Resistor
8.2.2.3
Gate Driver Output Resistor
8.2.2.4
Gate to Source Resistor Selection
8.2.2.5
Estimate Gate Driver Power Loss
8.2.2.6
Estimating Junction Temperature
8.2.2.7
Selecting VCCI, VDDA/B Capacitor
8.2.2.7.1
Selecting a VCCI Capacitor
8.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
8.2.2.7.3
Select a VDDB Capacitor
8.2.2.8
Dead Time Setting Guidelines
8.2.2.9
Application Circuits with Output Stage Negative Bias
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Certifications
11.4
Receiving Notification of Documentation Updates
11.5
Support Resources
11.6
Trademarks
11.7
Electrostatic Discharge Caution
11.8
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DWK|14
MPCS001
DW|16
MSOI003I
Thermal pad, mechanical data (Package|Pins)
DW|16
QFND505A
Orderable Information
sluset9g_oa
sluset9g_pm
1
Features
Universal: dual low-side, dual high-side or half-bridge driver
AEC-Q100 qualified with the following result
Device temperature grade 1
Junction temperature range –40 to +150°C
Up to 4A peak source and 6A peak sink output
Common-mode transient immunity (CMTI) greater than 125V/ns
Up to 25V VDD output drive supply
5V,
8V,
12V
and 17V
VDD UVLO options
Switching parameters:
33ns typical propagation delay
5ns maximum pulse-width distortion
10µs maximum VDD power-up delay
UVLO protection for all power supplies
Fast enable for power sequencing