SLUSDX3C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.5 Fault Modes

Occasionally, different fault conditions occur and the UCC25800-Q1 transformer driver protects the system from more severe damage by entering the following fault modes.

Table 8-5 Fault Mode Summary
FAULTDESCRIPTION
Overcurrent (OCP1)OCP1 occurs when the current in the internal low-side MOSFET during the low-side MOSFET on time exceeds IOCP for 2.1 ms. UCC25800B-Q1 disables the OCP1 fault action.
Overcurrent (OCP2)OCP2 occurs when the current in either MOSFET exceeds five times of the IOCP for more than 100 ns. UCC25800B-Q1 keeps the same OCP2 setting and fault action as UCC25800-Q1.
Over temperature (TSD)Over temperature protection (TSD) occurs when the junction temperature goes above TSD threshold.
Input overvoltageInput overvoltage protection occurs when VCC voltage is above the overvoltage shut-down (OVSD) threshold for more than 1.3 μs.
OC/DT openOC/DT open protection occurs if the OC/DT pin exceeds 4.5 V after the OCP check has been completed.
OC/DT shortOC/DT short protection occurs if the OC/DT pin falls below 500 mV.
OC/DT out of rangeOC/DT out-of-range protection occurs when the OC/DT pin voltage is between 3.95 V and 4.5 V during the OCP programming check.
RT shortRT short protection occurs when RT pin is below 150 mV.
OTP errorOTP error fault occurs when, during the OTP reading at start-up, the OTP sanity check fails. In case of OTP error fault, only OTP error fault code is transmitted while all other faults are ignored. The OTP error fault can be cleared only with a power cycle that forces a new OTP reading.

When any fault occurs the switching is immediately (after individual detection delays) stopped. The DIS/FLT pin is internally pulled down. After the fault codes are transmitted, the transformer driver current consumption is reduced to IVCCDIS. The VREG regulator remains enabled and the RT pin remains at its programmed level.

When the transformer driver enters fault mode it pulses the pull-down current on the DIS/FLT pin on and off to output a fault code and signal which fault has been triggered as explained in Section 8.3.6.1.

After a delay time of 100 ms, the DIS/FLT pin is released and, if it is not pulled low externally. When it crosses the ENTH, the transformer driver is enabled, the power up sequence occurs and the switching can start again. Before starting switching, the faults are checked again. If the protection that caused the fault condition still presents, or a new protection is triggered, the switching is not started and a new fault condition is asserted; fault codes are transmitted again. And the transformer driver current consumption is reduced to IVCCDIS. This fault and power-up sequence is automatically cycled until all the faults are cleared.