SLUSCE9B June   2017  – March 2020 UCC27712

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Propagation Delay Comparison
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Under Voltage Lockout
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Level Shift
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 7.3.7 Parasitic Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum Input Pulse Operation
      2. 7.4.2 Output Interlock and Dead Time
      3. 7.4.3 Operation Under 100% Duty Cycle Condition
      4. 7.4.4 Operation Under Negative HS Voltage Condition
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 8.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 8.2.2.6 Selecting Bootstrap Diode
        7. 8.2.2.7 Estimate the UCC27712 Power Losses (PUCC27712)
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Operation With IGBT's
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VDD and Under Voltage Lockout

The UCC27712 has an internal under voltage-lockout (UVLO) protection feature on the supply circuit blocks between VDD and VSS pins, as well as between HB and HS pins. When VDD bias voltage is lower than the VVDD(on) threshold at device start-up or lower than VVDD(off) after start-up, the VDD UVLO feature holds both the LO and HO outputs low, regardless of the status of the HI and LI inputs. On the other hand, if HB-HS bias supply voltage is lower than the VVHB(on) threshold at start-up or VVHB(off) after start-up, the HB-HS UVLO feature only holds HO to low, regardless of the status of the HI. The LO output status is not affected by the HB-HS UVLO feature (see Table 1 and Table 2). This allows the LO output to turn-on and re-charge the HB-HS capacitor using the boot-strap circuit and thus allows HB-HS bias voltage to surpass the VVHB(on) threshold.

Both the VDD and VHB UVLO protection functions are provided with a hysteresis feature. This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept a small drop in the bias voltage which is bound to happen when the device starts switching and quiescent current consumption increases instantaneously, as well as when the boot-strap circuit charges the HB-HS capacitor during the first instance of LO turn-on causing a drop in VDD voltage.

The UVLO circuit of VDD-VSS and HB-HS in UCC27712 generate internal signals to enable/disable the outputs after UVLO_ON/UVLO_OFF thresholds are crossed respectively (please refer to Figure 30). Design considerations indicate that the UVLO propagation delay before the outputs are enabled and disabled can vary from 20 μs to 50 μs.

Table 1. VDD UVLO Feature Logic Operation

CONDITION (VHB-VHS>VVHB, ON FOR ALL CASES BELOW) HI LI HO LO
VDD-VSS < VVDD(on) during device start up H L L L
VDD-VSS < VVDD(on) during device start up L H L L
VDD-VSS < VVDD(on) during device start up H H L L
VDD-VSS < VVDD(on) during device start up L L L L
VDD-VSS < VVDD(off) after device start up H L L L
VDD-VSS < VVDD(off) after device start up L H L L
VDD-VSS < VVDD(off) after device start up H H L L
VDD-VSS < VVDD(off) after device start up L L L L

Table 2. VHB UVLO Feature Logic Operation

CONDITION (VDD-VSS > VVDD,ON FOR ALL CASES BELOW) HI LI HO LO
VHB-VHS < VVHB(on) during device start up H L L L
VHB-VHS < VVHB(on) during device start up L H L H
VHB-VHS < VVHB(on) during device start up H H L L
VHB-VHS < VVHB(on) during device start up L L L L
VHB-VHS < VVHB(off) after device start up H L L L
VHB-VHS < VVHB(off) after device start up L H L H
VHB-VHS < VVHB(off) after device start up H H L L
VHB-VHS < VVHB(off) after device start up L L L L
UCC27712 powerup_lusby6.gifFigure 30. Power-Up Driver