This example illustrates the design process and component selection for a continuous mode power factor correction boost converter utilizing the UCC28180. The pertinent design equations are shown for a universal input, 360-W PFC converter with an output voltage of 390 V.

9.2.2.1 Current Calculations

The input fuse, bridge rectifier, and input capacitor are selected based upon the input current calculations. First, determine the maximum average output current, I_OUT(max):

Equation 4.

Equation 5.

The maximum input RMS line current, I_{IN_RMS(max)}, is calculated using the parameters from Table 1 and the efficiency and power factor initial assumptions:

Equation 6.

Equation 7.

Based upon the calculated RMS value, the maximum input current, I_{IN (max)}, and the maximum average input current, I_{IN_AVG(max)}, assuming the waveform is sinusoidal, can be determined.

Equation 8.

Equation 9.

Equation 10.

Equation 11.

9.2.2.2 Switching Frequency

The UCC28180 switching frequency is user programmable with a single resistor on the FREQ pin to ground. For this design, the switching frequency, f_SW, was chosen to be 120 kHz. Figure 30 (same as Figure 1) could be used to select the suitable resistor to program the switching frequency or the value can be calculated using constant scaling values of f_TYP and R_TYP. In all cases, f_TYP is a constant that is equal to 65 kHz, R_INT is a constant that is equal to 1 MΩ, and R_TYP is a constant that is equal to 32.7 kΩ. Simply applying the calculation below yields the appropriate resistor that should be placed between FREQ and GND:

Equation 12.

Equation 13.

A typical value of 17.8 kΩ for the FREQ resistor results in a switching frequency of 118 kHz.

Figure 30. Frequency vs. R_FREQ

9.2.2.3 Bridge Rectifier

The input bridge rectifier must have an average current capability that exceeds the input average current. Assuming a forward voltage drop, V_{F_BRIDGE}, of 1 V across the rectifier diodes, BR1, the power loss in the input bridge, P_BRIDGE, can be calculated:

Equation 14.

Equation 15.

Heat sinking will be required to maintain operation within the bridge rectifier’s safe operating area.

9.2.2.4 Inductor Ripple Current

The UCC28180 is a Continuous Conduction Mode (CCM) controller but if the chosen inductor allows relatively high-ripple current, the converter will be forced to operate in Discontinuous Mode (DCM) at light loads and at the higher input voltage range. High-inductor ripple current has an impact on the CCM/DCM boundary and results in higher light-load THD, and also affects the choices for the input capacitor, R_SENSE and C_ICOMP values. Allowing an inductor ripple current, ΔI_RIPPLE, of 20% or less will result in CCM operation over the majority of the operating range but requires a boost inductor that has a higher inductance value and the inductor itself will be physically large. As with all converter designs, decisions must be made at the onset in order to optimize performance with size and cost. In this design example, the inductor is sized in such a way as to allow a greater amount of ripple current in order to minimize space with the understanding that the converter operates in DCM at the higher input voltages and at light loads but optimized for a nominal input voltage of 115 V_AC at full load. Although specifically defined as a CCM controller, the UCC28180 is shown in this application to meet the overall performance goals while transitioning into DCM at high-line voltage, at a higher load level.

9.2.2.5 Input Capacitor

The input capacitor must be selected based upon the input ripple current and an acceptable high frequency input voltage ripple. Allowing an inductor ripple current, ΔI_RIPPLE, of 40% and a high frequency voltage ripple factor, ΔV_{RIPPLE_IN}, of 7%, the maximum input capacitor value, C_IN, is calculated by first determining the input ripple current, I_RIPPLE, and the input voltage ripple, V_{IN_RIPPLE}:

Equation 16.

Equation 17.

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

The recommended value for the input x-capacitor can now be calculated:

Equation 24.

Equation 25.

A standard value 0.33-µF Y2/X2 film capacitor is used.

9.2.2.6 Boost Inductor

Based upon the allowable inductor ripple current discussed above, the boost inductor, L_BST, is selected after determining the maximum inductor peak current, I_{L_PEAK}:

Equation 26.

Equation 27.

The minimum value of the boost inductor is calculated based upon the acceptable ripple current, I_RIPPLE, at a worst case duty cycle of 0.5:

Equation 28.

Equation 29.

The recommended minimum value for the boost inductor assuming a 40% ripple current is 321 µH; the actual value of the boost inductor that will be used is 327 µH. With this actual value used, the actual resultant inductor current ripple will be:

Equation 30.

Equation 31.

Equation 32.

Equation 33.

The duty cycle is a function of the rectified input voltage and will be continuously changing over the half line cycle. The duty cycle, DUTY_(max), can be calculated at the peak of the minimum input voltage:

Equation 34.

Equation 35.

Equation 36.

9.2.2.7 Boost Diode

The diode losses are estimated based upon the forward voltage drop, V_F, at 125°C and the reverse recovery charge, Q_RR, of the diode. Using a silicon carbide Schottky diode, although more expensive, will essentially eliminate the reverse recovery losses and result in less power dissipation:

Equation 37.

Equation 38.

Equation 39.

Equation 40.

This output diode should have a blocking voltage that exceeds the output over voltage of the converter and be attached to an appropriately sized heat sink.

9.2.2.8 Switching Element

The MOSFET/IGBT switch will be driven by a GATE output that is clamped at 15.2 V for VCC bias voltages greater than 15.2 V. An external gate drive resistor is recommended to limit the rise time and to dampen any ringing caused by the parasitic inductances and capacitances of the gate drive circuit; this will also help in meeting any EMI requirements of the converter. The design example uses a 3.3-Ω resistor; the final value of any design is dependent upon the parasitic elements associated with the layout of the design. To facilitate a fast turn off, a standard 40-V, 1-A Schottky diode is placed anti-parallel with the gate drive resistor. A 10-kΩ resistor is placed between the gate of the MOSFET/IGBT and ground to discharge the gate capacitance and protect from inadvertent dv/dt triggered turn-on.

The conduction losses of the switch MOSFET, in this design are estimated using the R_DS(on) at 125°C, found in the device data sheet, and the calculated drain to source RMS current, I_{DS_RMS}:

Equation 41.

Equation 42.

Equation 43.

Equation 44.

Equation 45.

The switching losses are estimated using the rise time, tr, and fall time, t_f, of the MOSFET gate, and the output capacitance losses.

Equation 46. t_r=5 ns

Equation 47.

Equation 48. t_r=5 ns

Total FET losses

Equation 49.

The MOSFET requires an appropriately sized heat sink.

9.2.2.9 Sense Resistor

To accommodate the gain of the non-linear power limit, the sense resistor, R_SENSE, is sized such that it triggers the soft over current at 10% higher than the maximum peak inductor current using the minimum soft over current threshold of the ISENSE pin, V_SOC, of ISENSE equal to 0.265 V.

Equation 50.

Equation 51.

The power dissipated across the sense resistor, P_RSENSE, must be calculated:

Equation 52.

Equation 53.

The peak current limit, PCL, protection feature is triggered when current through the sense resistor results in the voltage across R_SENSE to be equal to the V_PCL threshold. For a worst case analysis, the maximum V_PCL threshold is used:

Equation 54.

Equation 55.

To protect the device from inrush current, a standard 220-Ω resistor, R_ISENSE, is placed in series with the ISENSE pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin.

9.2.2.10 Output Capacitor

The output capacitor, C_OUT, is sized to meet holdup requirements of the converter. Assuming the downstream converters require the output of the PFC stage to never fall below 300 V, V_{OUT_HOLDUP(min)}, during one line cycle, t_HOLDUP = 1/f_LINE(min), the minimum calculated value for the capacitor is:

Equation 56.

Equation 57.

It is advisable to de-rate this capacitor value by 10%; the actual capacitor used is 270 µF.

Verifying that the maximum peak-to-peak output ripple voltage will be less than 5% of the output voltage ensures that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. If the output ripple voltage is greater than 5% of the regulated output voltage, a larger output capacitor is required. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor is calculated:

Equation 58.

Equation 59.

Equation 60.

Equation 61.

The required ripple current rating at twice the line frequency is equal to:

Equation 62.

Equation 63.

There is a high frequency ripple current through the output capacitor:

Equation 64.

Equation 65.

The total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly:

Equation 66.

Equation 67.

9.2.2.11 Output Voltage Set Point

For low power dissipation and minimal contribution to the voltage set point, it is recommended to use 1 MΩ for the top voltage feedback divider resistor, R_FB1. Multiple resistors in series are used due to the maximum allowable voltage across each. Using the internal 5-V reference, V_REF, the bottom divider resistor, R_FB2, is selected to meet the output voltage design goals.

Equation 68.

Equation 69.

A standard value 13-kΩ resistor for R_FB2 results in a nominal output voltage set point of 391 V.

An output over voltage is detected when the output voltage exceeds its nominal set-point level by 5%, as measured when the voltage at VSENSE is 105% of the reference voltage, V_REF. At this threshold, the enhanced dynamic response (EDR) is triggered and the non-linear gain to the voltage error amplifier will increase the transconductance to VCOMP and quickly return the output to its normal regulated value. This EDR threshold occurs when the output voltage reaches the V_OUT(ovd) level:

Equation 70.

Equation 71.

Equation 72.

In the event of an extreme output over voltage event, the GATE output will be disabled if the output voltage exceeds its nominal set-point value by 9%. The output voltage, V_OUT(ovp), at which this protection feature is triggered is calculated as follows:

Equation 73.

An output under voltage is detected when the output voltage falls below 5% below its nominal set-point as measured when the voltage at VSENSE is 95% of the reference voltage, V_REF:

Equation 74.

Equation 75.

Equation 76.

A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that the RC time constant is limited to approximately 10 µs so as not to significantly reduce the control response time to output voltage deviations.

Equation 77.

The closest standard value of 820 pF was used on VSENSE for a time constant of 10.66 µs.

9.2.2.12 Loop Compensation

The current loop is compensated first by determining the product of the internal loop variables, M₁M₂, using the internal controller constants K₁ and K_FQ. Compensation is optimized maximum load and nominal input voltage, 115 V_AC is used for the nominal line voltage for this design:

Equation 78.

Equation 79.

Equation 80.

The VCOMP operating point is found on the following chart, M₁M₂ vs. VCOMP. Once the M₁M₂ result is calculated above, find the resultant VCOMP voltage at that operating point to calculate the individual M₁ and M₂ components.

Figure 31. M1M2 vs. VCOMP

For the given M₁M₂ of 0.751 V/µs, the VCOMP approximately equal to 3 V, as shown in Figure 31.

The individual loop factors, M₁ which is the current loop gain factor, and M₂ which is the voltage loop PWM ramp slope, are calculated using the following conditions:

The M₁ non-linear current loop gain factor follows the following identities:

Equation 81. if V_COMP < 1 V

Equation 82. if 1 V < V_COMP < 2 V

Equation 83. if 2 V < V_COMP < 4.5 V

Equation 84. if 4.5 V < V_COMP < 5 V

In this example, according to the chart in Figure 31, VCOMP is approximately equal to 3 V, so M1 is calculated to be approximately equal to 0.366:

Equation 85.

The M₂ non-linear PWM ramp slope will obey the following relationships:

Equation 86. if V_COMP ≤ 0.5 V

Equation 87. if 0.5 V ≤ V_COMP ≤ 4.6 V

Equation 88. if 4.6 V ≤ V_COMP ≤ 5 V

In this example, with VCOMP approximately equal to 3 V, M₂ equals 1.388 V/µs:

Equation 89.

Verify that the product of the individual gain factors, M₁ and M₂, is approximately equal to the M₁M₂ factor determined above, if not, iterate the VCOMP value and recalculate M₁M₂

Equation 90.

The product of M₁ and M₂ is within 1% of the M₁M₂ factor previously calculated:

Equation 91.

Equation 92.

If more accuracy was desired, iteration results in a VCOMP value of 3.004 V where M₁M₂ and M₁ x M₂ are both equal to 0.751 V/µs.

The non-linear gain variable, M₃, can now be calculated:

Equation 93. if V_COMP < 5 V

Equation 94. if 0.5 V < V_COMP < 1 V

Equation 95. if 1 V < V_COMP < 2 V

Equation 96. if 2 V < V_COMP < 4.5 V

Equation 97. if 4.5 V < V_COMP < 4.6 V

Equation 98. if 4.6 V < V_COMP < 5 V

In this example, using 3.004 V for VCOMP for a more precise calculation, M₃ calculates to 1.035 V/µs:

Equation 99.

For designs that allow a high inductor ripple current, the current averaging pole, which functions to flatten out the ripple current on the input of the PWM comparator, should be at least decade before the converter switching frequency. Analysis on the completed converter may be needed to determine the ideal compensation pole for the current averaging circuit as too large of a capacitor on ICOMP will add phase lag and increase i_THD where as too small of an I_COMP capacitor will result in not enough averaging and an unstable current averaging loop. The frequency of the current averaging pole, f_IAVG, is chosen to be at approximately 5 kHz for this design as the current ripple factor, ∆I_RIPPLE, was chosen at the onset of the design process to be 40%, which is large enough to force DCM operation and result in relatively high inductor ripple current. The required capacitor on ICOMP, C_ICOMP, for this is determined using the transconductance gain, g_mi, of the internal current amplifier:

Equation 100.

Equation 101.

A standard value 2700-pF capacitor for C_ICOMP results in a current averaging pole frequency of 4.314 kHz.

Equation 102.

The transfer function of the current loop can be plotted:

Equation 103.

Equation 104.

Figure 32. Bode Plot of the Current Averaging Circuit

The voltage transfer function, G_VL(f) contains the product of the voltage feedback gain, G_FB, and the gain from the pulse width modulator to the power stage, G_{PWM_PS}, which includes the pulse width modulator to power stage pole, f_{PWM_PS}. The plotted result is shown in Figure 32.

Equation 105.

Equation 106.

Equation 107.

Equation 108.

Figure 33. Bode Plot of the Open Voltage Loop without Error Amplifier

The voltage error amplifier is compensated with a zero, f_ZERO, at the f_{PWM_PS} pole and a pole, f_POLE, placed at 20 Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, f_V, is desired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.

Equation 109.

Equation 110.

Equation 111.

From Figure 33, the gain of the voltage transfer function at 10 Hz is approximately 0.081 dB. Estimating that the parallel capacitor, C_{VCOMP_P}, is much smaller than the series capacitor, C_VCOMP, the unity gain will be at f_V, and the zero will be at f_{PWM_PS}, the series compensation capacitor is determined:

Equation 112.

Equation 113.

Equation 114.

The capacitor for VCOMP must have a voltage rating that is greater than the absolute maximum voltage rating of the VCOMP pin, which is 7 V. The readily available standard value capacitor that is rated for at least 10 V in the package size that would fit the application was 4.7 µF and this is the value used for C_VCOMP in this design example.

R_VCOMP is calculated using the actual C_VCOMP capacitor value.

Equation 115.

Equation 116.

Equation 117.

A 22.6-kΩ resistor is used for R_VCOMP.

Equation 118.

Equation 119.

A 0.47-µF capacitor is used for C_{VCOMP_P}.

The total closed loop transfer function, G_{VL_total}, contains the combined stages and is plotted in Figure 34.

Equation 120.

Equation 121.

Figure 34. Closed Loop Voltage Bode Plot