SLUSCR9B June   2017  – December 2020 UCC28730-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 HV (High Voltage Startup)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CBC (Cable Compensation)
        6. 7.3.1.6 VS (Voltage Sense)
        7. 7.3.1.7 CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-By Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CVDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1  Capacitance Terms in Farads
        2. 11.1.1.2  Duty-Cycle Terms
        3. 11.1.1.3  Frequency Terms in Hertz
        4. 11.1.1.4  Current Terms in Amperes
        5. 11.1.1.5  Current and Voltage Scaling Terms
        6. 11.1.1.6  Transformer Terms
        7. 11.1.1.7  Power Terms in Watts
        8. 11.1.1.8  Resistance Terms in Ω
        9. 11.1.1.9  Timing Terms in Seconds
        10. 11.1.1.10 DC Voltage Terms in Volts
        11. 11.1.1.11 AC Voltage Terms in Volts
        12. 11.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.6 VDD Capacitance, CVDD

A capacitor is required on VDD to provide:

  1. Run-state bias current during start-up while VDD falls toward UVLO, until VOCC is reached,
  2. Wait-state bias current between steady-state low-frequency power cycles and
  3. Wait-state bias current between minimum-frequency power cycles while VOUT recovers from a transient overshoot.

Generally, the value to satisfy (3) also satisfies (2) and (1), however the value for (1) may be the largest if the converter must provide high output current at a voltage below VOCC during power up.

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation, VOCC. At that point, the auxiliary winding can sustain the bias voltage to the UCC28730-Q1 above the UVLO shutdown threshold. The total current available to charge the output capacitors and supply an output load and is the constant-current regulation target, IOCC.

Equation 25 assumes that all of the output current of the flyback is available to charge the output capacitance until the minimum output voltage is achieved. For margin, there is an estimated 1 mA of average gate-drive current added to the run current and 1 V added to the minimum VDD.

Equation 25. GUID-0AAF2B5E-5B9C-4FB6-BEC8-3479F7AD1F71-low.gif

At light loads, the UCC28730-Q1 enters a Wait-state between power cycles to minimize bias power and improve efficiency. Equation 26 estimates the minimum capacitance needed to obtain a target maximum ripple voltage on VDD (VVDD(maxΔ) < 1 V, for example) during the Wait state, which occurs at the lowest possible switching frequency.

Equation 26. GUID-B6F28119-0A02-495A-8C4B-680C33BA88E7-low.gif

Choose the largest value of the previous CVDD calculations for the minimum VDD capacitance.