ACF contains two energy storage devices on primary and secondary sides. One is the clamping capacitor (C_CLAMP) and the other is the output capacitor. When the PWMH signal is enabled, the clamping capacitor voltage (V_CLAMP) is close to the reflected output voltage (N_PS x V_O). When the PWMH is disabled in LPM mode, V_CLAMP becomes higher, because some of the leakage energy will be stored on C_CLAMP , instead of recycling to the output, as it does in AAM and ABM. During the control mode transition from LPM to ABM, the capacitor voltage balancing current in the first PWMH on time is normally bigger than the following PWMH pulses. If the PWMH on time is too short to discharge C_CLAMP, a high di/dt change of the switching current will flow through the transformer winding at the turn-off instant of the high side switch, so the leakage inductance will introduce a high voltage stress across the secondary-side rectifier. Instead of using a strong RC snubber to damp the voltage spike or a lossy bleed resistor in parallel with C_CLAMP, UCC28782 automatically extends the first PWMH pulse width around 140% longer than the following PWMH pulse. When the high side switch turns off at lower di/dt current instance, the voltage stress can be reduced, and the efficiency compromise can be eliminated with this new voltage balancing function. Moreover, another possibility of triggering the on-time extension function is under the output voltage ramp down condition, which is a very common transient event of a USB-PD adapter. If the USB-PD controller on the secondary side is able to program the step size of the reference output voltage change, the LPM-to-ABM transition will occur during the voltage change. This behavior allows the V_CLAMP to follow the reflected output voltage change, and minimize the voltage stress on the rectifier.

However, some USB-PD controllers can not smoothly change the reference output voltage, but only offer a one-step voltage change to a lower reference level. This rapid change prevents the controller from switching in general, so the chance of voltage balancing during voltage transition is gone. Once the output voltage is settled to the lower level and PWMH is enabled back again, a big voltage difference between V_CLAMP and the reflected voltage occurs, and the magnitude of the balancing current may be large enough to create a high voltage stress and damage the secondary rectifier. In order to resolve this issue, UCC28782 utilizes a patent pending unique switching pattern in the survival mode to achieve the capacitor voltage balancing, as shown in the following figure.

With a rapid reference voltage (V_REF(Vo)) change, the feedback current (i_FB) increases and the controller enters into SBP1 mode. Since this event is like an output overshoot condition, the output voltage feedback loop prevents the ACF from switching and V_VDD drops. When V_VDD reaches the 13-V survival mode threshold, the unique burst packet contains a series of PWML pulses followed by a long PWMH pulse. The PWML pulse train helps to charge up the bootstrap capacitor voltage, so that the high-side switch can respond to the PWMH command. When the PWMH is in on state, the unbalanced voltage between V_CLAMP and the reflected V_BIN forces the additional energy to charge up C_BIN. The charge current becomes a useful energy source to keep V_VDD away from V_VDD(OFF). At the same time, C_CLAMP can be discharged gradually. Through the multiple survival mode events, V_CLAMP can be discharged to be very close to the reflected output voltage, so the voltage stress can be reduced. The minimum number of PWML pulses of the first survival-mode event is 9. The rest survival-mode burst packets contain at least 3 PWML pulses.

Figure 8-33 Capacitor Balancing During Output Voltage Transition