Table 2. Design Specification

9.2.1.2.1 Input Stage (R_F, D2, D3, C1, C2, L2)

• Resistor R_F is a flame-proof fusible resistor. R_F limits the inrush current, and also provide protection in case any component failure causes a short circuit. Value for its resistance is generally selected between 4.7 Ω to 15 Ω.
• A half-wave rectifier is chosen and implemented by diode D2 (1N4937). It is a general purpose 1-A, 600-V rated diode. It has a fast reverse recovery time (200 ns) for improved differential-mode-conducted EMI noise performance. Diode D3 (1N4007) is a general purpose 1-A, 1-kV rated diode with standard reverse recovery time (>500 ns), and is added for improved common-mode-conducted EMI noise performance. D3 can be removed and replaced by a short if not needed.
• EMI filtering is implemented by using a single differential-stage filter (C1-L2-C2).

Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage (VIN). The required input capacitor size can be calculated according Equation 2.

Equation 2.

where

• C_BULK(min) is minimum value for the total input capacitor value (C1 + C2 in the schematic of Figure 16).
• RCT = 1 in case of half wave rectifier and RCT = 2 in case of full-wave rectifier .
• P_IN is the converter input power.
• V_IN(min) is the minimum RMS value of the AC input voltage.
• V_BULK(min) is the minimum allowed voltage value across bulk capacitor during converter operation.
• f_LINE(min) is the minimum line frequency when the line voltage is V_IN(min).
• The converter maximum output power is: P_OUT = I_OUT x V_OUT = 0.225 A x 13 V = 2.925 W
• Assuming the efficiency η = 68% the input power is P_IN = P_OUT/η = 4.178 W
• V_BULK(min) = 80 V
• V_IN(min) = 85 V_RMS (from design specification table)
• f_LINE(min) = 57 Hz

C_BULK(min) = 15.6 μF. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% of tolerance in value, the minimum nominal value required for C_BULK is:

Equation 3.

Select C1 and C2 to be 10 μF each (C_BULK = 10 μF + 10 μF = 20 μF > C_BULKn(min)).

By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.

9.2.1.2.2 Regulator Capacitor (C_VDD)

Capacitor C_VDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-V rated ceramic capacitor is enough for proper operation of the device's internal LDO.

9.2.1.2.3 Freewheeling Diode (D1)

The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (t_rr).

The maximum reverse voltage that the diode should experience in the application, during normal operation, is given by Equation 4.

Equation 4.

A margin of 20% is generally considered.

The use of a fast recovery diode is required for the buck-freewheeling rectifier. When designed in CCM, the diode reverse recovery time should be less than 35 ns to keep low reverse recovery current and the switching loss. For example, STTH1R06A provides 25-ns reverse recovery time. When designed in DCM, slower diode can be used, but the reverse recovery time should be kept less than 75 ns. MURS160 can fit the requirement.

9.2.1.2.4 Output Capacitor (C_L)

The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value and equivalent series resistor (R_ESR). A larger capacitor value also has an impact on the start-up time. For a typical application, the capacitor value can start from 47 μF, to hundreds of μF. A guide for sizing the capacitor value can be calculated by the following equations:

Equation 5.

Equation 6.

Take into account that both C_L and R_ESR contribute to output voltage ripple. A first pass capacitance value can be selected and the contribution of C_L and R_ESR to the output voltage ripple can be evaluated. If the total ripple is too high the capacitance value has to increase or R_ESR value must be reduced. In the application example C_L was selected (330 µF) and it has an R_ESR of 0.03 Ω. So the R_ESR contributes for 4% of the total ripple. The formula that calculates C_L is based on the assumption that the converter operates in burst of twenty switching cycles. The number of bursts per cycle could be different, the formula for C_L is a first approximation.

9.2.1.2.5 Pre-Load Resistor (R_L)

The pre-load resistor connected at the output is required for the high-side buck topology. Unlike low side buck topology, the output voltage is directly sensed, in high-side buck topology the output is sampled and estimated. At no-load condition, because the feedback loop runs with its own time constant, the buck converter operates with a fixed minimum switching frequency. Select the pre-load resistor or using a zener diode to prevent output voltage goes too high at no-load condition.

A simple zener diode would be a good choice without going through the calculation. Besides the simplifying the calculation, zener diode doesn't consumes power at heavy load condition, which helps to improve the converter heavy-load efficiency.

A simple resistor can also be used to limit the output voltage at no load condition. However, this resistor connects to the output all the time and it reduces the full-load efficiency. The pre-load resistor can be calculated based on below equation or based on experiments. In this equation, the V_MAX is allowed maximum output voltage, and V_REG is the regulated output voltage.

Equation 7.

9.2.1.2.6 Inductor (L1)

Initial calculations:

Half of the peak-to-peak ripple current at full load:

Equation 8.

When operating in DCM, the peak-to-peak current ripple is the peak current of the device.

Average MOSFET conduction minimum duty cycle at continuous conduction mode is:

Equation 9.

If the converter operates in discontinuous conduction mode:

Equation 10.

Maximum allowed switching frequency at V_IN(max) and full load:

Equation 11.

Switching frequency has a maximum value limit of f_SW(max).

The worst case I_LIMIT = 315 mA, but assuming ΔI_L = 180 mA.

The converter works in continuous conduction mode (ΔI_L < I_LIMIT) so based on V_OUT = 13 V, V_d = 0.5 V and V_IN(max) = 375 V

Equation 12.

The maximum allowed switching frequency is 62 kHz because the calculated value exceeds it.

Equation 13.

The duty cycle does not force the MOSFET on time to go below t_{ON_TO}. If D_MIN/T_{ON_TO} < f_SW(max), the switching frequency is reduced by current runaway protection and the maximum average switching frequency is lower than f_SW(max), the converter can't support full load.

The minimum inductance value satisfies both the following conditions:

Equation 14.

Equation 15.

In the application example, 1 mH is selected as the minimum standard value that satisfy Equation 14 and Equation 15.

9.2.1.2.7 Feedback Path (C_FB, R_FB1 and R_FB2) and Load Resistor (R_L)

In low-side buck converter the output voltage is always sensed by the FB pin and UCC28881 internal controller can turn on the MOSFET on VOUT. In high-side buck converter applications the information on the output voltage value is stored on C_FB capacitor. This information is not updated in real time. The information on C_FB capacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor current forces the freewheeling diode (D1 in Figure 16) to turn on and the GND pin of UCC28881 goes negative at -V_d1 (where V_d1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 in Figure 16). When D1 is on, through diode D4, the C_FB capacitor is charged at V_OUT – V_d4 + V_d1. Set the output voltage regulation level using Equation 16.

Equation 16.

where

• V_{FB_TH} is the FB pin reference voltage.
• V_{OUT_T} is the target output voltage.
• R_FB1, R_FB2 is the resistance of the resistor divider connected with FB pin (see Figure 16)
• The capacitor C_FB after D1 is discharged with a time constant that is τ_FB = C_FB x (R_FB1 + R_FB2 ).
• Select the time constant τ_FB, given in Equation 17

Equation 17.

In this equation, R_LOAD is the full load resistor value.

The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In order to reduce the output-voltage increase, increase τ_FB. The drawback of increasing τ_FB is t in high-load conditions V_OUT could drop.

Because of the nature of sample and hold of output voltage feedback, the feedback loop components need some adjustment after the initial design. The larger time constant of the feedback components leads to lower no-load switching frequency. As the results, the no-load standby power and light-load voltage regulation are improved. Because of larger time constant, at heavier load, the load regulation start to get worse. On the contrast, decreasing the time constant makes the heavy load regulation better but increases the no-load standby power and makes the light-load voltage regulation worse. Some tradeoff is required to make the regulation and standby power. Below table summarizes the relationship between the feedback loop time constant and the load regulation. This can be used for an easy guideline for fine tuning the circuit performance.

Table 4. Converter Efficiency

Table 5. Key Component List for 13-V 225-mA High-Side Buck Converter