SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)

The HV Startup circuit utilizes two 600-V depletion mode MOSFETs (Q1, Q2). The depletion mode MOSFET conducts when no gate voltage is applied and begins to turn off as the VGS voltage becomes more and more negative. It is completely off when VGS is below the turn-off threshold. The characteristics of the depletion mode FET make it well suited to implementing a current source for high-voltage startup. It is difficult to find a low-cost and small-size depletion MOSFET with 1.2-kV rating, but there are wide variety of selection in 600-V to 800-V domain. Therefore, the stacked depletion MOSFET configuration with the proposed gate clamp circuit will evenly distribute the voltage stress from the 1-kV input voltage.

First, let’s look at the operation of Q1. Notice the four 130-V Zener diodes; D2, D4, D6 and D8. Their combined Zener voltage is 520 V. Next, think of R1 as a pull-up resistor to VIN that simply provides current to the Zener diodes. With that in mind, it’s obvious that these diodes will be off if VIN < 520 V. Now, as VIN rises above 520 V, the voltage at the source of Q1 will be clamped slightly above 520 V, let’s say 521 V. In effect Q1 is biased such that the maximum voltage presented to Q2 is limited to 521 V. The VDS voltage of Q1 is VIN – 520 V. At 1000 VIN, the VDS of Q2 will be 521 V and VDS of Q1 will be 479 V.

Next, let’s look at the operation of Q2. For now, let’s say D5 is a 22-V “safety” clamp to limit the maximum value of VDD in the event Q3 does not turn on. So, for normal operation it’s practical to assume D5 is off. When VDD < VDD_ON, Q3 is also off because the controller has not been powered up yet and VREF = 0 V. R3 is a pull-up resistor (similar to R1 for Q1) that biases D9 on in the forward direction during HV startup. The majority of current flows from the source of Q2 through R5 and charges the 22-µF capacitor on VDD (C12). We can use KVL around the loop formed by R3, D9, and R5 and solve for the current through R5.

Equation 29. I R 5 = ( V F ( D 9 ) + V G S ) R 5

Typical values for VF_D9 and VGS=VTH_Q2 are 0.3 V and 1.0 V, respectively. With this information we can solve for IR5

Equation 30. I R 5 = ( 0.3 V + 1.0 V ) 1 k Ω = 1.3   m A

Notice this current does not depend on VIN so it will be constant over the entire range of VIN.

If a soft start time requirement is provided (tSS,MAX) the maximum value of R5 (R5MAX) can be calculated.

Equation 31. R 5 M A X =   V T H _ Q 2 + V F _ D 9 C V D D × V D D O N t S S , M A X + I S U _ U C C 28 C 5 x

Q3 functions as a simple switch controlled by VREF from the controller to shut down the HV startup circuit. When Q3 turns on zener diode D9 is reverse biased and clamps the VGS voltage of Q2 to about ‒18 V. Shutting down the HV startup circuit when it is not needed reduces power and improves efficiency.

This HV startup circuit is presented in detail and compared to traditional NPN-based HV startup circuit in “High-Density 40W Auxiliary Power Supply Utilizing a SiC MOSFET for 800-V Traction Inverters”, SLUAAL3.