SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.14.1 Power Stage Gain, Poles, and Zeroes

The typical power stage of the DCM flyback has a single zero and a single pole. The zero is created by the ESR of the output capacitors and the output capacitance. The pole is created by the load resistance and the output capacitance. When the load changes the pole shifts in frequency as 1/RLOAD. The power stage will introduce the most phase loss when the load is relatively low and RLOAD is high. Therefore, it is best to stabilize the system and check the stability margins at low VIN, high VIN, light-load, and maximum load.

Start by calculating the location of the power-stage zero

Equation 32. f Z E R O = 1 2 × π × C O U T × E S R C O U T = 1 2 × π × 2000 µ F × 16.5 m Ω = 4.8   k H z

Next, calculate the pole location with about 120 % of maximum load, 3.24 A load (RLOAD = 4.6 Ω)

Equation 33. f P O L E = 1 2 × π × C O U T × R L O A D = 1 2 × π × 2000 µ F × 4.6 Ω = 17   H z

In this application, the feedback voltage is formed from an auxiliary winding. This feedback path contains a 22-µF capacitor (C12) and a 4.7-µF capacitor (C13) that introduce another (atypical) low frequency pole. The pole is formed by the total capacitance (C12+C13) and the equivalent load current of the regulator. The equivalent load of the regulator is the sum of the operating supply current (IVDD, 1.3 mATYP) and the gate drive current to the MOSFET (QG x fSW, 11 nC x 42.5 kHz = 0.47 mA). The VDD voltage is typically 18.6 V, so the equivalent resistance can be modelled as 18.6 V / 1.77 mA = 10.5 kΩ.

The following figure shows the frequency response of the plant characteristic (a.k.a. COMP-to-output response). It compares the DCM flyback both with and without the pole formed by AUX components, 22 µF + 4.7 µF / 10.5 kΩ. Notice the response with the AUX components is ~15dB lower with an additional 45 deg of phase loss at 1.0 kHz.

Figure 9-3 Comparison of DCM Flyback Plant with and without AUX Components