SLUSFG5 November 2024 UCC33421-Q1
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
The UCC33421-Q1 has soft-start mechanism that ensures a smooth and fast soft-start operation with minimum input inrush current. The output voltage Soft-Start diagram is shown in Figure 7-1. After VINP > VVINP_UVLO_R and EN/FLT is pulled high, the soft-start sequence starts with a primary duty cycle open loop control. The power stage operates with a fixed burst frequency with an incremental increasing duty cycle starting at 6.5% . The rate of change of the duty cycle is pre-programmed in the part to reduce the input inrush current while building the output voltage VCC. The primary side limits the maximum duty cycle to 62.5% during this phase till the secondary side VCC voltage passes VVCC_UVLO = 2.7V threshold before releasing this duty cycle limit. This limit will ensure minimum input current in case the device starts on a short circuit and the VCC is not building up.
The soft-start time will vary depending on the output capacitors, input voltage and loading conditions. The UCC33421-Q1 has a soft-start timeout feature by which the VCC output voltage state is monitored during soft-start. In certain conditions the VCC might not reach steady-state regulation threshold due to short circuit on the output voltage as shown in Figure 7-2 , heavy loading conditions above recommended operating conditions or higher output capacitor values as shown in Figure 7-3. In these conditions, if the soft-start timout duration of 16ms expires without the VCC reaching steady-state regulation, the part will shutdown and EN/FLT pin will be pulled low for 200us to report the fault condition. An auto-restart timer will start afterwards, the part will attempt to restart after that timer expires. More details regarding fault reporting and auto-restart can be found in Fault Reporting and Auto-Restart. If the same conditions continue to exist the same cycle will repeat again as shown in Figure 7-2and Figure 7-3 below.