SLUSG03 December   2024 UCC57102Z-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Driver Stage
      3. 6.3.3 Desaturation (DESAT) Protection
      4. 6.3.4 Fault (FLT)
      5. 6.3.5 VREF
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.1 VDD Undervoltage Lockout

The UCC57102Z-Q1 device offers an undervoltage lockout threshold of 8 V and the UCC57102Z-Q1 provides an undervoltage lockout threshold of 12V. The device's hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 1V of typical UVLO hysteresis is expected. There is no significant driver output turnon delay due to the UVLO feature, and 4 μs of UVLO delay is expected. The UVLO turn-off delay is also minimized as much as possible. The UVLO delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of the input pins and enable pin. The device accepts a wide range of slew rates on its VDD pin, and VDD noise within the hysteresis range does not affect the output state of the driver (neither ON nor OFF).

UCC57102Z-Q1 Power UpFigure 7-2 Power Up