6.3.1 CPU Memory Map and interruptions

When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:

Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as follows:

The registers and bit definitions inside the system and peripheral blocks are detailed in the programmer’s guide for each peripheral.

6.3.2 Boot ROM

The UCD3138A incorporates a 4k boot ROM. This boot ROM includes support for:

• Program download through the PMBus
• Device initialization
• Examining and modifying registers and memory
• Verifying and executing program FLASH automatically
• Jumping to a customer defined boot program

The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash. This permits full automated program memory checking, when there is no need for a custom boot program.

If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface

These functions can be used to read and write to all memory locations in the UCD3138A. Typically they are used to download a program to Program Flash, and to command its execution

6.3.3 Customer Boot Program

It is possible to generate a user boot program using 2 kB or more of the program flash. This program can support features which the Boot ROM does not support, including:

• Program download via UART. This program is useful especially for applications where the UCD3138A is isolated from the host (for example, PFC)
• Encrypted download. This program is useful for code security in field updates.

6.3.4 Flash Management

The UCD3138A offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware stores multiple copies of system parameters in data flash. This is minimizes the risk of losing information if programming is interrupted.

6.4.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are writable in the ARM privilege mode only to enable user mode protection.

6.4.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space decoding.

6.4.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.

6.4.4 Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interruptions by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The request channels are maskable, allowing individual channels to be selectively disabled or enabled.

6.5.1 Sync FET Ramp and IDE Calculation

The UCD3138A has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comes in two forms:

• Sync FET ramp
• Ideal Diode Emulation (IDE) calculation

When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly, it may pull down the prebias voltage, causing the power supply to sink current.

To avoid this, Sync FETs are not turned on until the power supply has ramped up to the nominal voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramp logic can be used to turn them on at a rate below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the Sync FETs is a function of V_IN, V_OUT, and the primary side duty cycle (D). The IDE logic in the UCD3138A takes V_IN and V_OUT data from the firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync FETs.

6.5.2 Automatic Mode Switching

Automatic Mode switching enables the DPWM module to switch between modes automatically. This is useful to increase efficiency and power range. The following paragraphs describe phase-shifted full bridge and LLC examples:

6.5.2.1 Phase Shifted Full Bridge Example

Phase shifted full bridge topologies are shown in Figure 6-1 and Figure 6-2.

Figure 6-1 Phase Shifted Full Bridge

Figure 6-2 Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification

6.5.2.2 LLC Example

In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:

Figure 6-3 Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification

6.5.2.3 Mechanism for Automatic Mode Switching

The UCD3138A allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.

If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown in Figure 6-4.

Figure 6-4 Automatic Mode Switching

As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point.

6.5.3 DPWMC, Edge Generation, IntraMux

The UCD3138A has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.

DPWMC is an auxillary signal inside the DPWM logic. It can be generated using the Blanking A begin time, and the Blanking A end time.

The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can output a generated edge.

The options are:

0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge

Where “n" is the numerical index of the DPWM module of interest. For example n = 1 refers to DPWM1.

The Edge Gen is controlled by the DPWMEDGEGEN register.

The IntraMux (short for intra multiplexer) is controlled by the Auto Config registers. The IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are controlled with automatic mode switching. When disabled, DPWMA and DPWMB are driven as described in the Section 6.5.2 section. If the Intra Mux is enabled, the high-resolution feature must be disabled, and the DPWM edge resolution falls to 4 ns.

The Edge Gen/Intra Mux is shown in Figure 6-5.

Figure 6-5 Edge Gen/Intra Mux

A list of the IntraMux modes for DPWMA is as follows:

0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)

0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)

The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:

6.5.4 Filter

The UCD3138A filter is a PID filter with many enhancements for power supply control. Some of its features include:

• Traditional PID Architecture
• Programmable non-linear limits for automated modification of filter coefficients based on received EADC error
• Multiple coefficient sets fully configurable by firmware
• Full 24-bit precision throughout filter calculations
• Programmable clamps on integrator branch and filter output
• Ability to load values into internal filter registers while system is running
• Ability to stall calculations on any of the individual filter branches
• Ability to turn off calculations on any of the individual filter branches
• Duty cycle, resonant period, or phase shift generation based on filter output.
• Flux balancing
• Voltage feed forward

Figure 6-6 First Section of the Filter

The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole.

The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve transient response.

Tthe output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits) is shown in Figure 6-7

Figure 6-7 Output Section of the Filter

This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.

The final section for the filter, which permits its output to be matched to the DPWM is shown in Figure 6-8.

Figure 6-8 Final Section for the Filter

This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode, the filter can be used to generate both period and duty cycle.

Figure 6-9 Resonant Mode

6.5.4.2 Fault Multiplexer

In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138A provides an extensive array of multiplexers that are united under the name Fault Mux module.

The Fault Mux Module supports flexible mapping between fault sources and fault response mechanism inside each DPWM module.

• Many fault sources can be mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A.
• A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules.

The Fault Mux Module provides a multitude of fault protection functions within the UCD3138A high-speed loop (front end control, filter, DPWM and loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module.

Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module.

The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the output it affects under a fault condition.

Figure 6-10 Fault Module

All fault modules are capable of detecting faults only once per DPWM switching cycle. Each one of the fault modules have a separate max_count value and the device sets the fault flag only when the sequential faults count exceeds the max_count value.

After the fault flag is set, DPWMs must be disabled by DPWM_EN going low in order to clear the fault flags.

NOTE

All four fault modules share the same DPWM_EN control. The device clears all fault flags (output of fault modules) simultaneously.

All four Fault Modules share the same global FAULT_EN as well. Therefore, a specific Fault Module cannot be enabled/ disabled separately.

Figure 6-11 Cycle by Cycle Block

In contrast to the fault modules, only one cycle by cycle block is available in each DPWM module.

The cycle by cycle block can work in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from analog peak current mode (PCM) module.

The fault Mux module supports the following basic functions:

• 4 digital comparators with programmable thresholds and fault generation
• Configuration for 7 high-speed analog comparators with programmable thresholds and fault generation
• External GPIO detection control with programmable fault generation
• Configurable DPWM fault generation for DPWM current limit fault, DPWM overvoltage detection fault, DPWM A external fault, DPWM B external fault and DPWM IDE flag
• Clock failure detection for high and low frequency oscillator blocks
• Discontinuous conduction mode detection

Figure 6-12 Fault Mux Block Diagram

6.5.5 Communication Ports

6.5.5.2 PMBus Interfacte

The PMBus Interface supports independent master and slave modes controlled directly by firmware through a processor bus interface. Individual control and status registers enable firmware to send or receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I²C Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol Specification (PMBus 1.3).

The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface connects directly to the I²C/SMBus/PMBus Clock, Data, Alert, and Control signals.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies I_BIAS to each address detect pin and the voltage on that pin is captured by the internal 12-bit ADC.

R_ADDSET is the resistor that sets the PMBus address. Bin(V_AD0x) is the address bin for one of 12 address as shown in Figure 6-13.

Figure 6-13 PMBus Address Detection Method

6.5.5.3 General Purpose ADC12

The ADC12 is a 12-bit, high speed analog-to-digital converter, equipped with the following options:

• Typical conversion speed of 267 ksps
• Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
• Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
• Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIG pin or Analog Comparator results
• Interrupt capability to embedded processor at completion of ADC conversion
• Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or averaged ADC data
• Two 10 µA current sources for excitation of PMBus addressing resistors
• Dual sample and hold for accurate power measurement
• Internal temperature sensor for temperature protection and monitoring

The control module ADC12 Contol Block Diagram contains the control and conversion logic for auto-sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channels can be sampled in any desired order or programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical Characteristics plots for the temperature variation associated with this function.

Figure 6-14 ADC12 Control Block Diagram

6.5.6 Miscellaneous Analog

The Miscellaneous Analog Control (MAC) Registers provide control and monitor a wide variety of functions. These functions include device supervisory features such as brown-out and power saving configuration, general purpose input and output configuration and interfacing, internal temperature sensor control and current sharing control.

The MAC module provides trim signals to the oscillator and AFE blocks. These controls are usually used at the time of trimming at manufacturing; therefore this data sheet does not include any descriptions of these trim controls.

The MAC registers and peripherals are all available in the 64-pin version. Other UCD3138A devices may have reduced resources. See also the Section 3 section.

6.5.7 Package ID Information

Package ID register includes information regarding the package type of the device and can be read by firmware for reporting through PMBus or for other package sensitive decisions.

6.5.8 Brownout

Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition that may be considered unsafe for proper operation of the device.

The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower than brownout threshold, it still does not necessarily trigger a device reset.

The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an interrupt service routine. See .

6.5.9 Global I/O

Up to 30 pins in the UCD3138A device can be configured to serve as a general purpose input or output pin (GPIO). This includes all digital input or output pins except for the RESET pin.

The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins, EADC analog input pins and the RESET pin.

There are two ways to configure and use the digital pins as GPIO pins:

• Through the centralized Global I/O control registers.
• Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO functionality.

The Global I/O registers offer full control of:

• Configuring each pin as a GPIO.
• Setting each pin as input or output.
• Reading the pin’s logic state, if it is configured as an input pin.
• Setting the logic state of the pin, if it is configured as an output pin.
• Configuring pin/pins as open drain or push-pull (Normal)

The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control Register, Global I/O Value Register and Global I/O Read Register.

The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:

Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.

6.5.10 Temperature Sensor Control

Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The internal temperature sensor is disabled as default.

Figure 6-15 Internal Temp Sensor

Temperature sensor is calibrated at room temperature (25°C) via a calibration register value.

The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement).

The temperature sensor can be enabled or disabled.

6.5.11 I/O Mux Control

In different packages of UCD3138A several I/O functions are multiplexed and routed toward a single physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be assigned to a physical device pin for your application.

6.5.12 Current Sharing Control

UCD3138A provides three separate modes of current sharing operation.

• Analog bus current sharing
• PWM bus current sharing
• Master/Slave current sharing
• AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus if power is missing from the UCD3138A

The simplified current sharing circuitry is shown in the drawing below:

Figure 6-16 Simplified Current Sharing Circuitry

The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be controlled through the current sharing control register (CSCTRL).

6.5.13 Temperature Reference

The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal temperature sensor (channel 14) during the factory trim and calibration.

This information can be used by different periodic temperature compensation routines implemented in the firmware. But it should not be overwritten by firmware, otherwise this factory written value is lost.