SLUS652E March   2005  – April 2020 UCD8220

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 UCD8220 Typical Simplified Push-Pull Converter Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation

UCD8220 iset_peak_slusb36.gifFigure 34. UCD8220 Configured in Peak Current Control with Internal Slope Compensation

When the ISET resistor is configured as shown in Figure 34 with the ISET resistor connected between the ISET pin and the AGND pin, the device is configured for peak current-mode control with internal slope compensation. The voltage at the ISET pin is 1.85 V so the internal slope compensation current, I_SC, being fed into the internal slope compensation capacitor is equal to 1.85 / (11 × R_ISET). Use Equation 7 to calculate the voltage slope at the PWM comparator input which is generated by this current.

Equation 7. UCD8220 q3_slope_slusb36.gif
UCD8220 slope_v_riset_lus65.gifFigure 35. Slope vs R_ISET Resistance

The amount of slope compensation required depends on the design of the power stage and the output specifications. A general rule is to add an up-slope equal to the down slope of the output inductor. Refer to (1) and (8) in the Related Documentation section for a more detailed discussion regarding slope compensation in peak current mode controlled power stages.