SNAS304H January 2006 – April 2016 ADC121S101 , ADC121S101-Q1
PRODUCTION DATA.
The ADC121S101 is a low-power, single-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S101 is fully specified over a sample rate range of 500 ksps to 1 Msps. The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit.
The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces.
The ADC121S101 operates with a single supply with a range from 2.7 V to 5.25 V. Normal power consumption using a 3 V or 5 V supply is 2 mW and 10 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a 5-V supply.
The ADC121S101 is packaged in 6-pin WSON and SOT-23 packages. Operation over the temperature range of −40°C to 125°C is specified.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC121S101 | WSON (6) | 2.50 mm × 2.20 mm |
SOT-23 (6) | 2.90 mm × 1.60 mm |
Changes from G Revision (January 2014) to H Revision
Changes from F Revision (May 2013) to G Revision
Changes from E Revision (May 2013) to F Revision
RESOLUTION | SPECIFIED SAMPLE RATE RANGE | ||
---|---|---|---|
50 TO 200 KSPS | 200 TO 500 KSPS | 500 KSPS TO 1 MSPS | |
12 Bits | ADC121S021 | ADC121S051 | ADC121S101 |
10 Bits | ADC101S021 | ADC101S051 | ADC101S101 |
8 Bits | ADC081S021 | ADC081S051 | ADC081S101 |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VA | P | Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin. |
2 | GND | G | The ground return for the supply and signals. |
3 | VIN | I | Analog input. This signal can range from 0 V to VA. |
4 | SCLK | I | Digital clock input. This clock directly controls the conversion and readout processes. |
5 | SDATA | O | Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. |
6 | CS | I | Chip select. On the falling edge of CS, a conversion process begins. |
PAD | GND | G | For package suffix CISD(X) only. TI recommends connecting the center pad to ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Analog supply voltage, VA | –0.3 | 6.5 | V | |
Voltage on any digital pin to GND | –0.3 | 6.5 | V | |
Voltage on any analog pin to GND | –0.3 | VA + 0.3 | V | |
Input current at any pin(4) | ±10 | mA | ||
Package input current(4) | ±20 | mA | ||
Power consumption at TA = 25°C | See(5) | |||
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3500 | V |
Machine model (MM) | ±300 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±3500 | V | |
Charged-device model (CDM), per AEC Q100-011, all pins | ±300 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VA | Supply voltage | 2.7 | 5.25 | V | |
Digital input pins voltage (regardless of supply voltage) | –0.3 | 5.25 | V | ||
Analog input pins voltage | 0 | VA | V | ||
Clock frequency | 25 | 20000 | kHz | ||
Sample rate | Up to 1 Msps |
||||
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADC121S101 | UNIT | ||
---|---|---|---|---|
NGF (WSON) | DBV (SOT-23) | |||
6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 94 | 265 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 118 | 151 | °C/W |
RθJB | Junction-to-board thermal resistance | 69 | 30 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.5 | 30 | °C/W |
ψJB | Junction-to-board characterization parameter | 69 | 29 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 15 | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
STATIC CONVERTER | |||||||
Resolution with no missing codes | VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C | 12 | Bits | ||||
INL | Integral non-linearity | –40°C ≤ TA ≤ 85°C, VA = 2.7 V to 3.6 V |
SOT-23 | –1 | ±0.4 | 1 | LSB |
WSON | –1.2 | ±0.4 | 1 | ||||
TA = 125°C, VA = 2.7 V to 3.6 V |
SOT-23 | –1.1 | 1 | ||||
WSON | –1.3 | 1 | |||||
DNL | Differential non-linearity | –40°C ≤ TA ≤ 85°C, VA = 2.7 V to 3.6 V | 0.5 | 1 | LSB | ||
–0.9 | –0.3 | ||||||
TA = 125°C, VA = 2.7 V to 3.6 V | –1 | 1 | |||||
VOFF | Offset error | –40°C ≤ TA ≤ 125°C, VA = 2.7 V to 3.6 V | –1.2 | ±0.1 | 1.2 | LSB | |
GE | Gain error | –40°C ≤ TA ≤ 125°C, VA = 2.7 V to 3.6 V |
SOT-23 | –1.2 | ±0.2 | 1.2 | LSB |
WSON | –1.5 | ±0.2 | 1.5 | ||||
DYNAMIC CONVERTER | |||||||
SINAD | Signal-to-noise plus distortion ratio | VA = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 125°C fIN = 100 kHz, –0.02 dBFS |
70 | 72 | dB | ||
SNR | Signal-to-noise ratio | VA = 2.7 V to 5.25 V, –40°C ≤ TA ≤ 85°C fIN = 100 kHz, –0.02 dBFS |
70.8 | 72.5 | dB | ||
VA = 2.7 V to 5.25 V, TA = 125°C fIN = 100 kHz, –0.02 dBFS |
70.6 | ||||||
THD | Total harmonic distortion | VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS |
–80 | dB | |||
SFDR | Spurious-free dynamic range | VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS |
82 | dB | |||
ENOB | Effective number of bits | VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS, –40°C ≤ TA ≤ 125°C |
11.3 | 11.6 | Bits | ||
IMD | Intermodulation distortion, second order terms |
VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz | –78 | dB | |||
Intermodulation distortion, third order terms |
VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz | –78 | dB | ||||
FPBW | –3-dB full power bandwidth | VA = 5 V | 11 | MHz | |||
VA = 3 V | 8 | ||||||
ANALOG INPUT | |||||||
VIN | Input range | 0 to VA | V | ||||
IDCL | DC leakage current | –40°C ≤ TA ≤ 125°C | –1 | 1 | µA | ||
CINA | Input capacitance | Track mode | 30 | pF | |||
Hold mode | 4 | ||||||
DIGITAL INPUT | |||||||
VIH | Input high voltage | VA = 5.25 V, –40°C ≤ TA ≤ 125°C | 2.4 | V | |||
VA = 3.6 V, –40°C ≤ TA ≤ 125°C | 2.1 | ||||||
VIL | Input low voltage | VA = 5 V, –40°C ≤ TA ≤ 125°C | 0.8 | V | |||
VA = 3 V, –40°C ≤ TA ≤ 125°C | 0.4 | ||||||
IIN | Input current | VIN = 0 V or VA, –40°C ≤ TA ≤ 125°C | –1 | ±0.1 | 1 | µA | |
CIND | Digital input capacitance | –40°C ≤ TA ≤ 125°C | 2 | 4 | pF | ||
DIGITAL OUTPUT | |||||||
VOH | Output high voltage | ISOURCE = 200 µA, –40°C ≤ TA ≤ 125°C | VA – 0.2 | VA – 0.07 | V | ||
ISOURCE = 1 mA | VA – 0.1 | ||||||
VOL | Output low voltage | ISINK = 200 µA, –40°C ≤ TA ≤ 125°C | 0.03 | 0.4 | V | ||
ISINK = 1 mA | 0.1 | ||||||
IOZH, IOZL | TRI-STATE leakage current | –40°C ≤ TA ≤ 125°C | –10 | ±0.1 | 10 | µA | |
COUT | TRI-STATE output capacitance | –40°C ≤ TA ≤ 125°C | 2 | 4 | pF | ||
Output coding | Straight (natural) binary | ||||||
POWER SUPPLY | |||||||
VA | Supply voltage | –40°C ≤ TA ≤ 125°C | 2.7 | 5.25 | V | ||
IA | Supply current, normal mode (operational, CS low) |
VA = 5.25 V, fSAMPLE = 1 Msps, –40°C ≤ TA ≤ 125°C |
2.0 | 3.2 | mA | ||
VA = 3.6 V, fSAMPLE = 1 Msps, –40°C ≤ TA ≤ 125°C |
0.6 | 1.5 | |||||
Supply current, shutdown (CS high) |
fSCLK = 0 MHz, VA = 5 V, fSAMPLE = 0 ksps | 500 | nA | ||||
fSCLK = 20 MHz, VA = 5 V, fSAMPLE = 0 ksps | 60 | µA | |||||
PD | Power consumption, normal mode (operational, CS low) |
VA = 5 V, –40°C ≤ TA ≤ 125°C | 10 | 16 | mW | ||
VA = 3 V, –40°C ≤ TA ≤ 125°C | 2.0 | 4.5 | |||||
Power consumption, shutdown (CS high) |
fSCLK = 0 MHz, VA = 5 V, fSAMPLE = 0 ksps | 2.5 | µW | ||||
fSCLK = 20 MHz, VA = 5 V, fSAMPLE = 0 ksps | 300 | ||||||
AC | |||||||
fSCLK | Clock frequency(3) | –40°C ≤ TA ≤ 125°C(4) | 10 | 20 | MHz | ||
fS | Sample rate | –40°C ≤ TA ≤ 125°C(4) | 500 | 1000 | ksps | ||
DC | SCLK duty cycle | fSCLK = 20 MHz, –40°C ≤ TA ≤ 125°C | 40% | 50% | 60% | ||
tACQ | Minimum time required for acquisition | –40°C ≤ TA ≤ 125°C | 350 | ns | |||
tQUIET | Quiet time | –40°C ≤ TA ≤ 125°C(5) | 50 | ns | |||
tAD | Aperture delay | 3 | ns | ||||
tAJ | Aperture jitter | 30 | ps |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCS | Minimum CS pulse width | –40°C ≤ TA ≤ 125°C | 10 | ns | ||
tSU | CS to SCLK setup time | –40°C ≤ TA ≤ 125°C | 10 | ns | ||
tEN | Delay from CS until SDATA TRI-STATE disabled(1) | –40°C ≤ TA ≤ 125°C | 20 | ns | ||
tACC | Data access time after SCLK falling edge(2) | VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C |
40 | ns | ||
VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C |
20 | |||||
tCL | SCLK low pulse width | –40°C ≤ TA ≤ 125°C | 0.4 × tSCLK | ns | ||
tCH | SCLK high pulse width | –40°C ≤ TA ≤ 125°C | 0.4 × tSCLK | ns | ||
tH | SCLK to data valid hold time | VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C |
7 | ns | ||
VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C |
5 | |||||
tDIS | SCLK falling edge to SDATA high impedance(3) | VA = 2.7 V to 3.6 V, –40°C ≤ TA ≤ 125°C |
6 | 25 | ns | |
VA = 4.75 V to 5.25 V, –40°C ≤ TA ≤ 125°C |
5 | 25 | ||||
tPOWER-UP | Power-up time from full power down | 1 | µs |
The ADC121S101 is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter core. Simplified schematics of the ADC121S101 in both track and hold modes are shown in Figure 16 and Figure 17, respectively. In Figure 16, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode.
Figure 17 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.
See the Functional Block Diagram for the serial interface timing diagram for the ADC. CS is chip select, which initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK are labelled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2). The interval for the tACQ specification begins at this point. At least 350 ns must pass between the 13th rising edge of SCLK and the next falling edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again to begin another conversion.
Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC produces three leading zero bits on SDATA, followed by twelve data bits, most significant first.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK.
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one conversion and the start of another. At the maximum specified SCLK frequency, the maximum guaranteed throughput is obtained by using a 20-SCLK frame. As shown in Figure 2, the minimum allowed time between CS falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls.
For example, at the fastest rate for this family of parts, SCLK is 20MHz and 2.5 SCLKs are 125 ns, so calculate the minimum time between CS falling edges using Equation 1.
(12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1 MSPS. At the slowest rate for this family, SCLK is 1 MHz. Using a 20 cycle conversion frame as shown in Figure 2 yields a 20-µs time between CS falling edges for a throughput of 50 KSPS.
It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a
1-MHz SCLK, there are 2500 ns in 2.5-SCLK cycles, which is greater than tACQ. After the last data bit has come out, the clock requires one full cycle to return to a falling edge. Thus the total time between falling edges of CS is
12.5 × 1 µs + 2.5 × 1 µs + 1 × 1 µs = 16 µs, which is a throughput of 62.5 KSPS.
The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC is VA/4096. Figure 18 shows the ideal transfer characteristic. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB.
Figure 19 shows an equivalent circuit for the ADC's input. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time must the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, the ESD diodes must not be used to clamp the input signal.
The capacitor C1 in Figure 19 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the track or hold switch, and is typically 500 Ω. Capacitor C2 is the ADC sampling capacitor and is typically 26 pF. The ADC delivers the best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter.
The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to 5.25 V with respect to GND, regardless of VA, the supply voltage. This allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage.
The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a sample rate as low as zero.
The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again.
Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 20. Once CS has been brought high in this manner, the device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line.
To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC begins powering up (see Timing Requirements for power-up time specifications). This power-up delay results in the first conversion result being unusable. The second conversion performed after power up, however, is valid, as shown in Figure 21.
If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC is fully powered up after 16 SCLK cycles.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Figure 22 shows a typical application of the ADC. In this example, power is provided by TI's LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network placed close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades the noise performance of the device. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown in Figure 22 connected to a microprocessor or DSP.
A positive supply-only, data acquisition system is capable of digitizing a single-ended input signal ranging from
0 V to 5 V with a throughput up to 1 Msps. The ADC121S101 must interface to an MCU whose supply is set at
5 V.
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from the fact that VA is also a reference potential for the ADC. The maximum sampling rate of the ADC121S101
Fs = FSCLK / 20.
Noise consideration must be given to the SPI interface, especially when the master MCU is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.
Take care when the signal source is capable of producing voltages beyond VA. In such instances, the internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action use Schottky diodes.
A 0.1-µF capacitor must be placed close to the supply pin of the ADC121S101.
A small capacitor (1 nF to 10 nF) placed on the input pin can help the internal sampling capacitor settle. If the ADC121S101 is driven by an operational amplifier, a small resistor (50 Ω to 200 Ω) must be placed between the output of the operational amplifier and the junction of the capacitor and the ADC121S101 input pin.
The power supply pin is bypassed with a capacitor network located close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance.
The ADC takes time to power up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC performs conversions properly. Note that the tQUIET time must still be included between the first dummy conversion and the second valid conversion.
When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As such, one dummy conversion must be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode.
When the ADC is operated continuously in normal mode, the maximum throughput is fSCLK / 20 at the maximum specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion. Figure 15 shows a plot of typical power consumption versus throughput. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power consumption vs throughput is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.
The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance causes voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents causes ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance.
To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100-Ω series resistor at the ADC output, placed as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improves noise performance.