SNAS304H January 2006 – April 2016 ADC121S101 , ADC121S101-Q1
PRODUCTION DATA.
The ADC121S101 is a low-power, single-channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S101 is fully specified over a sample rate range of 500 ksps to 1 Msps. The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit.
The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces.
The ADC121S101 operates with a single supply with a range from 2.7 V to 5.25 V. Normal power consumption using a 3 V or 5 V supply is 2 mW and 10 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a 5-V supply.
The ADC121S101 is packaged in 6-pin WSON and SOT-23 packages. Operation over the temperature range of −40°C to 125°C is specified.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC121S101 | WSON (6) | 2.50 mm × 2.20 mm |
SOT-23 (6) | 2.90 mm × 1.60 mm |
Changes from G Revision (January 2014) to H Revision
Changes from F Revision (May 2013) to G Revision
Changes from E Revision (May 2013) to F Revision
RESOLUTION | SPECIFIED SAMPLE RATE RANGE | ||
---|---|---|---|
50 TO 200 KSPS | 200 TO 500 KSPS | 500 KSPS TO 1 MSPS | |
12 Bits | ADC121S021 | ADC121S051 | ADC121S101 |
10 Bits | ADC101S021 | ADC101S051 | ADC101S101 |
8 Bits | ADC081S021 | ADC081S051 | ADC081S101 |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VA | P | Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin. |
2 | GND | G | The ground return for the supply and signals. |
3 | VIN | I | Analog input. This signal can range from 0 V to VA. |
4 | SCLK | I | Digital clock input. This clock directly controls the conversion and readout processes. |
5 | SDATA | O | Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. |
6 | CS | I | Chip select. On the falling edge of CS, a conversion process begins. |
PAD | GND | G | For package suffix CISD(X) only. TI recommends connecting the center pad to ground. |