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Data Sheet
ADC364x Dual-Channel, 14-Bit 250MSPS and
500MSPS Analog-to-Digital Converter (ADC)
1 Features
- 14-bit, dual channel 250 and 500MSPS ADC
- Noise spectral density: -158.5dBFS/Hz
- Thermal Noise: 74.5dBFS
- Single core (non-interleaved) ADC architecture
- Power consumption:
- 300mW/channel
(500MSPS)
- 250mW/channel
(250MSPS)
- Aperture jitter: 75fs
- Buffered analog inputs
- Programmable 100Ω to 200Ω
termination
- Input full scale: 2Vpp
- Full power input bandwidth (-3dB): 1.4GHz
- Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 84dBc
- SFDR worst spur: 90dBFS
- Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- DDR, Serial LVDS interface
- 14-bit Parallel DDR LVDS for DDC bypass
- 16-bit Serial LVDS for decimation
- 32-bit output option for high decimation
