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ADC3649

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14-bit two-channel 500MSPS ADC with LVDS interface and up to 32768x decimation

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Data sheet

ADC3649

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Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 600 Architecture Pipeline SNR (dB) 74 ENOB (Bits) 12 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 600 Architecture Pipeline SNR (dB) 74 ENOB (Bits) 12 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² 9 x 9
  • 14-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -158.5dBFS/Hz
  • Thermal Noise: 74.5dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 300mW/channel (500MSPS)
    • 250mW/channel (250MSPS)
    Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω to 200Ω termination
  • Input full scale: 2Vpp
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 73.8dBFS
    • SFDR HD2,3: 84dBc
    • SFDR worst spur: 90dBFS
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR, Serial LVDS interface
    • 14-bit Parallel DDR LVDS for DDC bypass
    • 16-bit Serial LVDS for decimation
    • 32-bit output option for high decimation
  • 14-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -158.5dBFS/Hz
  • Thermal Noise: 74.5dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 300mW/channel (500MSPS)
    • 250mW/channel (250MSPS)
    Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω to 200Ω termination
  • Input full scale: 2Vpp
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 73.8dBFS
    • SFDR HD2,3: 84dBc
    • SFDR worst spur: 90dBFS
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR, Serial LVDS interface
    • 14-bit Parallel DDR LVDS for DDC bypass
    • 16-bit Serial LVDS for decimation
    • 32-bit output option for high decimation

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.
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* Data sheet ADC364x Dual-Channel, 14-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet PDF | HTML 04 Dec 2024

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Evaluation board

ADC3669EVM — ADC3669 evaluation module

The ADC3669EVM is designed to evaluate the ADC3669 family of high-speed analog-to-digital converters (ADCs). The ADC3669EVM is populated with an ADC3669, a 16-bit dual-channel ADC with an LVDS interface that can operate at sample rates up to 500MSPS. The ADC3669EVM allows for evaluation of all (...)
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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