SLASEU7
March 2023
AFE781H1
,
AFE881H1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics: VOUT DAC
6.9
Typical Characteristics: ADC
6.10
Typical Characteristics: Reference
6.11
Typical Characteristics: HART Modem
6.12
Typical Characteristics: Power Supply
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Digital-to-Analog Converter (DAC) Overview
7.3.1.1
DAC Resistor String
7.3.1.2
DAC Buffer Amplifier
7.3.1.3
DAC Transfer Function
7.3.1.4
DAC Gain and Offset Calibration
7.3.1.5
Programmable Slew Rate
7.3.1.6
DAC Register Structure and CLEAR State
7.3.2
Analog-to-Digital Converter (ADC) Overview
7.3.2.1
ADC Operation
7.3.2.2
ADC Custom Channel Sequencer
7.3.2.3
ADC Synchronization
7.3.2.4
ADC Offset Calibration
7.3.2.5
External Monitoring Inputs
7.3.2.6
Temperature Sensor
7.3.2.7
Self-Diagnostic Multiplexer
7.3.2.8
ADC Bypass
7.3.3
Programmable Out-of-Range Alarms
7.3.3.1
Alarm-Based Interrupts
7.3.3.2
Alarm Action Configuration Register
7.3.3.3
Alarm Voltage Generator
7.3.3.4
Temperature Sensor Alarm Function
7.3.3.5
Internal Reference Alarm Function
7.3.3.6
ADC Alarm Function
7.3.3.7
Fault Detection
7.3.4
IRQ
7.3.5
HART Interface
7.3.5.1
FIFO Buffers
7.3.5.1.1
FIFO Buffer Access
7.3.5.1.2
FIFO Buffer Flags
7.3.5.2
HART Modulator
7.3.5.3
HART Demodulator
7.3.5.4
HART Modem Modes
7.3.5.4.1
Half-Duplex Mode
7.3.5.4.2
Full-Duplex Mode
7.3.5.5
HART Modulation and Demodulation Arbitration
7.3.5.5.1
HART Receive Mode
7.3.5.5.2
HART Transmit Mode
7.3.5.6
HART Modulator Timing and Preamble Requirements
7.3.5.7
HART Demodulator Timing and Preamble Requirements
7.3.5.8
IRQ Configuration for HART Communication
7.3.5.9
HART Communication Using the SPI
7.3.5.10
HART Communication Using UART
7.3.5.11
Memory Built-In Self-Test (MBIST)
7.3.6
Internal Reference
7.3.7
Integrated Precision Oscillator
7.3.8
One-Time Programmable (OTP) Memory
7.4
Device Functional Modes
7.4.1
DAC Power-Down Mode
7.4.2
Reset
7.5
Programming
7.5.1
Communication Setup
7.5.1.1
SPI Mode
7.5.1.2
UART Mode
7.5.1.3
SPI Plus UART Mode
7.5.1.4
HART Functionality Setup Options
7.5.2
Serial Peripheral Interface (SPI)
7.5.2.1
SPI Frame Definition
7.5.2.2
SPI Read and Write
7.5.2.3
Frame Error Checking
7.5.2.4
Synchronization
7.5.3
UART Interface
7.5.3.1
UART Break Mode (UBM)
7.5.3.1.1
Interface With FIFO Buffers and Register Map
7.5.4
Status Bits
7.5.5
Watchdog Timer
7.6
Register Maps
7.6.1
AFEx81H1 Registers
8
Application and Implementation
8.1
Application Information
8.1.1
Multichannel Configuration
8.2
Typical Application
8.2.1
4-mA to 20-mA Current Transmitter
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Start-Up Circuit
8.2.1.2.2
Current Loop Control
8.2.1.2.3
Input Protection and Rectification
8.2.1.2.4
System Current Budget
8.2.1.3
Application Curves
8.3
Initialization Set Up
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RRU|24
MPQF588
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slaseu7_oa
slaseu7_pm
1
Features
Functional Safety-Capable
Documentation available to aid functional safety system design:
AFE881H1
,
AFE781H1
Low quiescent current: 180 µA (typical)
HART®
-compliant physical layer modem
16-bit or 14-bit monotonic high-performance DAC
1.8-V supply: 0.15 V to 1.25 V, 0.2 V to 1.0 V
5-V supply: 0.3 V to 2.5 V, 0.4 V to 2.0 V
4-LSB INL at 16 bits
0.07% FSR (max) TUE from –40°C to +125°C
12-bit 3.84-kSPS ADC for advanced diagnostics
Integrated 1.25-V reference at 10 ppm/°C (max)
Internal 1.2288-MHz oscillator with clock output
Digital interface
Serial peripheral interface (SPI): Shared bus for both DAC and HART
Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART
Both: SPI for DAC and UART for HART
Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC
Digital DAC slew-rate control
Wide operating temperature: –55°C to +125°C