• Menu
  • Product
  • Email
  • PDF
  • Order now

  • AM5718-HIREL Sitara Processors Silicon Revision 2.0

    • SPRS999 August   2017 AM5718-HIREL

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • AM5718-HIREL Sitara Processors Silicon Revision 2.0
  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3  Device Comparison
    1. 3.1 Device Comparison Table
  4. 4  Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem - Video Output Ports
      3. 4.4.3  Display Subsystem - High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power On Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY-1.5 V and 1.8 V
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
      4. 7.23.4 GMAC RGMII Timings
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Single-Ended Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 QSPI Board Design and Layout Guidelines
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical Packaging and Orderable Information
  11. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZBO|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sprs999_oa
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

AM5718-HIREL Sitara Processors Silicon Revision 2.0

1 Device Overview

1.1 Features

  • For Silicon Revision 1.0 Information, See SPRS919
  • ARM® Cortex®-A15 Microprocessor Subsystem
  • C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible With C67x and C64x+
    • Up to Thirty-Two 16 × 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 512KB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • DDR3/DDR3L Memory Interface (EMIF) Module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB Across Single Chip Select
  • Dual ARM® Cortex®-M4 Coprocessors
  • IVA-HD Subsystem
  • Display Subsystem
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
    • Display Controller With DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2x Dual-Core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
  • Accelerator (BB2D) Subsystem
    • Vivante™ GC320 Core
  • Video Processing Engine (VPE)
  • Available Single-Core PowerVR® SGX544 3D GPU
  • One Video Input Port (VIP) Module
    • Support for up to Four Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • Ethernet Subsystem
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five High-Speed Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • SATA Gen2 Interface
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • High-Speed USB 2.0 Dual-Role Device
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC/SD/SDIO)
  • PCI Express® 3.0 Subsystems With Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • Or Two 1-Lane Gen2-Compliant Ports
  • Dual Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • MIPI® CSI-2 Camera Serial Interface
  • Up to 215 General-Purpose I/O (GPIO) Pins
  • Power, Reset, and Clock Management
  • On-Chip Debug With CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ZBO)

1.2 Applications

  • Industrial Communication
  • Human-Machine Interface (HMI)
  • Automation and Control
  • High-Performance Applications
  • Other General Use

1.3 Description

AM5718-HIREL Sitara ARM applications processors are built to meet the intense processing needs of the modern embedded products.

AM5718-HIREL devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by a single-core ARM Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The ARM processor lets developers keep control functions separate from vision algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the ARM and C66x DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The AM5718-HIREL Sitara ARM processor family is qualified according to the AEC-Q100 Standard.

Device Information

PART NUMBER PACKAGE BODY SIZE
AM5718-HIREL FCBGA (760) 23.00 mm × 23.00 mm

1.4 Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

AM5718-HIREL func_sprs919-002.gif Figure 1-1 AM5718-HIREL Block Diagram

2 Revision History

DATE REVISION NOTES
August 2017 * Initial release.

3 Device Comparison

3.1 Device Comparison Table

Table 3-1 shows a comparison between AM5718 devices, highlighting the differences. For a comparison of the full AM57xx family of devices, refer to Parametric Table.

Table 3-1 Device Comparison

FEATURES DEVICE
AM5718
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value(4) AM5718: 55 (0x37)
AM5718-E: 56 (0x38)
Processors/ Accelerators
Speed Grades X
ARM Single Cortex-A15 Microprocessor Subsystem (MPU) MPU core 0 Yes
C66x VLIW DSP DSP1 Yes
BitBLT 2D Hardware Acceleration Engine (BB2D) BB2D Yes
Display Subsystem VOUT1 Yes
VOUT2 Yes
VOUT3 Yes
HDMI Yes
Dual ARM Cortex-M4 Image Processing Unit (IPU) IPU1 Yes
IPU2(2) Yes
Image Video Accelarator (IVA) IVA Yes
SGX544 Single-Core 3D Graphics Processing Unit (GPU) GPU Yes
Video Input Port 1 (VIP1) vin1a Yes
vin1b Yes
vin2a Yes
vin2b Yes
Video Processing Engine (VPE) VPE Yes
Program/Data Storage
On-Chip Shared Memory (RAM) OCMC_RAM1 512KB
General-Purpose Memory Controller (GPMC) GPMC Yes
DDR3 Memory Controller EMIF1 Up to 2GB across single chip select
Dynamic Memory Manager (DMM) DMM Yes
Radio Support
Audio Tracking Logic (ATL) ATL Not Supported(1)
Viterbi Coprocessor (VCP) VCP1 Not Supported(1)
VCP2 Not Supported(1)
Peripherals
Dual Controller Area Network (DCAN) Interface DCAN1 Yes
DCAN2 Yes
Enhanced DMA (EDMA) EDMA Yes
System DMA (DMA_SYSTEM) DMA_SYSTEM Yes
Ethernet Subsystem (Ethernet SS) GMAC_SW[0] MII, RMII, or RGMII
GMAC_SW[1] MII, RMII, or RGMII
General Purpose I/O (GPIO) GPIO up to 215
Inter-Integrated Circuit (I2C) Interface I2C 5
System Mailbox Module MAILBOX 13
Media Local Bus Subsystem MLB Not Supported(1)
Camera Adaptation Layer (CAL) Camera Serial Interface 2 (CSI2) CSI2_0 Yes
CSI2_1 Yes
Multichannel Audio Serial Port (McASP) McASP1 16 serializers
McASP2 16 serializers
McASP3 4 serializers
McASP4 4 serializers
McASP5 4 serializers
McASP6 4 serializers
McASP7 4 serializers
McASP8 4 serializers
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO) MMC1 1x UHSI 4b
MMC2 1x eMMC 8b
MMC3 1x SDIO 8b
MMC4 1x SDIO 4b
PCI Express 3.0 Port with Integrated PHY PCIe_SS1 Up to two lanes (second lane shared with PCIe_SS2 and USB1)
PCIe_SS2 Single lane (shared with PCIe_SS1 and USB1)
2x Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) PRU-ICSS1 Yes
PRU-ICSS2 Yes
Serial Advanced Technology Attachment (SATA) SATA Yes
Real-Time Clock Subsystem (RTCSS)(3) RTCSS Yes
Multichannel Serial Peripheral Interface (McSPI) McSPI 4
HDQ1W HDQ1W Yes
Quad SPI (QSPI) QSPI Yes
Spinlock Module SPINLOCK Yes
Keyboard Controller (KBD) KBD Yes
Timers, General-Purpose TIMERS GP 16
Timer, Watchdog WD TIMER Yes
Pulse-Width Modulation Subsystem (PWMSS) PWMSS1 Yes
PWMSS2 Yes
PWMSS3 Yes
Universal Asynchronous Receiver/Transmitter (UART) UART 10
Universal Serial Bus (USB3.0) USB1 (SuperSpeed, Dual-Role-Device [DRD] Yes
Universal Serial Bus (USB2.0) USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY) Yes
USB3 (Highspeed, OTG2.0, with ULPI) Not Supported(1)
USB4 (Highspeed, OTG2.0, with ULPI) Not Supported(1)
  1. Features noted as “not supported,” must not be used. Their functionality is not supported by TI for this family of devices. These features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.
  2. IPU2 subsystem is dedicated to IVA support and is not available for other processing.
  3. RTC only mode is not supported feature.
  4. For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the AM571x Technical Reference Manual (SPRUHZ7).

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale