SLPS572 December   2015 CSD97396Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering CSD97396Q4M and Gate Drivers
      2. 7.3.2 Undervoltage Lockout (UVLO) Protection
      3. 7.3.3 PWM Pin
      4. 7.3.4 SKIP# Pin
        1. 7.3.4.1 Zero Crossing (ZX) Operation
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 SOA Curves
      3. 8.3.3 Normalized Curves
      4. 8.3.4 Calculating Power Loss and SOA
        1. 8.3.4.1 Design Example
        2. 8.3.4.2 Calculating Power Loss
        3. 8.3.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Community Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Over 93% System Efficiency at 15 A
  • Max Rated Continuous Current 30 A, Peak 65 A
  • High Frequency Operation (up to 2 MHz)
  • High Density – SON 3.5 mm × 4.5 mm Footprint
  • Ultra-Low Inductance Package
  • System-Optimized PCB Footprint
  • Ultra-Low Quiescent (ULQ) Current Mode
  • 3.3 V and 5 V PWM Signal Compatible
  • Diode Emulation Mode With FCCM
  • Input Voltages up to 24 V
  • Tri-State PWM Input
  • Integrated Bootstrap Diode
  • Shoot-Through Protection
  • RoHS Compliant – Lead Free Terminal Plating
  • Halogen Free

2 Applications

  • Ultrabook/Notebook DC/DC Converters
  • Multiphase Vcore and DDR Solutions
  • Point-of-Load Synchronous Buck in Networking, Telecom, and Computing Systems

3 Description

The CSD97396Q4M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density synchronous buck converter. This product integrates the driver IC and NexFET technology to complete the power stage switching function. The driver IC has a built-in selectable diode emulation function that enables DCM operation to improve light load efficiency. In addition, the driver IC supports ULQ mode that enables connected standby for Windows® 8. With the PWM input in tri-state, quiescent current is reduced to 130 µA, with immediate response. When SKIP# is held at tri-state, the current is reduced to 8 µA (typically 20 µs is required to resume switching). This combination produces a high current, high efficiency, and high speed switching device in a small 3.5 × 4.5 mm outline package. In addition, the PCB footprint is optimized to help reduce design time and simplify the completion of the overall system design.

Device Information(1)

ORDER NUMBER PACKAGE MEDIA AND QTY
CSD97396Q4M SON 3.5 × 4.5 mm
Plastic Package		 13-inch reel 2500
CSD97396Q4MT 7-inch reel 250
  1. For all available packages, see the orderable addendum at the end of the data sheet.

SPACER

Application Diagram

CSD97396Q4M Applications_Diagram_FP.gif

Typical Power Stage Efficiency and Power Loss

CSD97396Q4M D000_SLPS572_r3.gif