SLASF60 april 2023 DAC53204-Q1 , DAC63204-Q1
PRODUCTION DATA
The 12-bit DAC63204‑Q1 and 10-bit DAC53204‑Q1 (DACx3204‑Q1) are a pin-compatible family of automotive, quad-channel, buffered, voltage-output and current-output smart digital-to-analog converters (DACs). The DACx3204‑Q1 devices support Hi-Z power-down mode and Hi-Z output during power-off condition. The DAC outputs provide a force-sense option for use as a programmable comparator and current sink. The multifunction GPIO, function generation, and NVM enable these smart DACs for processor-less applications and design reuse. These devices automatically detect I2C, PMBus, and SPI and contain an internal reference.
The feature set combined with the tiny package and low power make these DACx3204‑Q1 smart DACs an excellent choice for applications such as voltage margining and scaling, dc set-point for biasing and calibration, and waveform generation.
PART NUMBER | RESOLUTION | PACKAGE(1) |
---|---|---|
DAC63204‑Q1 | 12 bit | RTE (WQFN, 16) |
DAC53204‑Q1 | 10 bit | RTE (WQFN, 16) |
DATE | REVISION | NOTES |
---|---|---|
april 2023 | * | Initial Release |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | FB3 | Input | Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current. |
2 | OUT3 | Output | Analog output voltage from DAC channel 3. |
3 | OUT2 | Output | Analog output voltage from DAC channel 2. |
4 | FB2 | Input | Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current. |
5 | GPIO/SDO | Input/Output | General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS. For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD. |
6 | SCL/SYNC | Output | I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external pullup resistor. This pin can ramp up before VDD. |
7 | A0/SDI | Input | Address
configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1). For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD. |
8 | SDA/SCLK | Input/Output | Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external pullup resistor in the I2C mode. This pin can ramp up before VDD. |
9 | FB1 | Input | Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current. |
10 | OUT1 | Output | Analog output voltage from DAC channel 1. |
11 | OUT0 | Output | Analog output voltage from DAC channel 0. |
12 | FB0 | Input | Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current. |
13 | CAP | Power | External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND. |
14 | AGND | Ground | Ground reference point for all circuitry on the device. |
15 | VDD | Power | Supply voltage. |
16 | VREF | Power | External
reference input. Connect a capacitor (approximately 0.1 μF) between
VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case an external reference is used, make sure the reference ramps up after VDD. |
— | Thermal Pad | Ground | Connect the thermal pad to AGND. |