DRV3205-Q1 Three-Phase Automotive Gate Driver With Three Integrated Current Shunt Amplifiers and Enhanced Protection, Diagnostics, and Monitoring
- SLVSCV1E September 2015 – February 2017 DRV3205-Q1
  
  PRODUCTION DATA.

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DATA SHEET

DRV3205-Q1 Three-Phase Automotive Gate Driver With Three Integrated Current Shunt Amplifiers and Enhanced Protection, Diagnostics, and Monitoring

1 Features

AEC-Q100 Qualified for Automotive Applications:
- Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
Three-Phase Bridge Driver for Motor Control
Suitable for 12-V and 24-V Applications
Three Integrated High-Accuracy Current Sense Amplifiers
Integrated Boost Converter, Gate Drive to 4.75 V
Drives 6 Separate N-Channel Power MOSFETs
Strong 1-A Gate Drive for High-Current FETs
Programmable Dead Time
PWM Frequency up to 20 kHz
Supports 100% Duty Cycle Operation
Short-Circuit Protection
- VDS-Monitoring (Adjustable Detection Level)
- Shunt Current Limit (Adjustable Detection Level)
Overvoltage and Undervoltage Protection
Overtemperature Warning and Shut Down
Sophisticated Failure Detection and Handling Through SPI
System Supervision
- Q&A Watchdog
- I/O Supply Monitoring
- ADREF Monitoring
Programmable Internal Fault Diagnostics
Sleep Mode Function
Thermally-Enhanced 48-Pin HTQFP PowerPAD™ IC Package (7-mm × 7-mm Body)

2 Applications

Automotive Motor-Control Applications
- Electrical Power Steering (EPS, EHPS)
- Electrical Brake and Brake Assist
- Transmission
- Pumps
Industrial Motor-Control Applications

3 Description

The DRV3205-Q1 bridge driver is dedicated to automotive three-phase brushless DC motor control applications. The device provides six dedicated drivers for standard-level N-channel MOSFET transistors. A boost converter with an integrated FET provides the overdrive voltage, allowing full control on the power stages even for low battery voltage down to 4.75 V. The strong driver strength is suitable for high-current applications and programmable to limit peak output current.

The device incorporates robust FET protection and system monitoring functions like a Q&A watchdog and voltage monitors for I/O supplies and ADC reference voltages. Integrated internal diagnostic functions can be accessed and programmed through an SPI interface.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DRV3205-Q1	HTQFP (48)	7.00 mm × 7.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

4 Revision History

Changes from D Revision (November 2016) to E Revision

Added the propagation delay graphs to the Typical Characteristics sectionGo
Changed the note on the Single 8-Bit SPI Frame/Transfer figureGo
Updated the Typical Application Diagram figureGo

Changes from C Revision (October 2016) to D Revision

Changed the maximum value for the RVSET resistor error detection parameter (4.4.31) from 1.5 to 1.4 kΩ in the Electrical Characteristics tableGo
Changed the units and symbol for the RVSET output voltage parameter (4.4.32–4.4.34), and fixed duplicate position number for T_J = 25°C and 125°C in the Electrical Characteristics tableGo
Added characterization note to parameters 5.7 and 5.29 through 5.30e in the Electrical Characteristics tableGo
Deleted the VS voltage range test condition from the boost output voltage parameter (6.1) in the Electrical Characteristics table Go
Added new test condition to the switching frequency parameter (6.3) and add new values for switching frequency at V_S < 6 (6.31) in the Electrical Characteristics tableGo
Changed the maximum value for the input pulldown resistor at EN pin parameter (7.4) from 300 to 360 kΩ in the Electrical Characteristics tableGo
Changed the position number for the output high and low voltage 2 parameters in the Electrical Characteristics table Go
Added characterization note to parameters 13.2 through 13.11 in the Serial Peripheral Interface Timing Requirements tableGo

Changes from B Revision (October 2016) to C Revision

Clarified the temperature for the BOOST pin quiescent current parameters (3.6B and 3.6C) and added new temperature condition (3.62B and 3.61C) in the Recommended Operating Conditions tableGo
Deleted the maximum value for the input hysteresis parameters (7.3 and 7.3A) in the Electrical Characteristics tableGo
Changed the values for the input pullup resistance parameter (7.5) in the Electrical Characteristics tableGo

Changes from A Revision (October 2016) to B Revision

Changed AEC-Q1100 to AEC-Q100 in the Features sectionGo
Changed the maximum value for the VCC5 and VCC3 short-to-ground current from 70 to 80 mA in the Absolute Maximum Ratings tableGo
Changed the minimum value for the high-side/low-side driver shutdown current parameter from 7 to 2 mA in the Electrical Characteristics tableGo

Changes from * Revision (September 2016) to A Revision

Changed the device status from Product Preview to Production Data Go

5 Pin Configuration and Functions

PHP PowerPAD™ Package

48-Pin HTQFP

Top View

Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NO.	NAME	TYPE⁽¹⁾	DESCRIPTION
1	GLS3	PWR	Gate low-side 3, connected to gate of external power MOSFET.
2	SLS3	PWR	Source low-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
3	GHS3	PWR	Gate high-side 3, connected to gate of external power MOSFET.
4	SHS3	PWR	Source high-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
5	VSH	HVI_A	Sense high-side, sensing VS connection of the external power MOSFETs for VDS monitoring.
6	SHS2	PWR	Source high-side 2, connected to external power MOSFET gate discharge and VDS monitoring.
7	GHS2	PWR	Gate high-side 2, connected to gate of external power MOSFET.
8	SLS2	PWR	Source low-side 2, connected to external power MOSFET for gate discharge and VDS monitoring.
9	GLS2	PWR	Gate low-side 2, connected to gate of external power MOSFET.
10	TEST	HVI_A	Test mode input, during normal application connected to ground.
11	GLS1	PWR	Gate low-side 1, connected to gate of external power MOSFET.
12	SLS1	PWR	Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring.
13	GHS1	PWR	Gate high-side 1, connected to gate of external power MOS transistor.
14	SHS1	PWR	Source high-side 1, connected to external power MOS transistor for gate discharge and VDS.
15	VS	Supply	Power-supply voltage (externally protected against reverse battery connection).
16	GNDA	GND	Analog ground.
17	ERR	LVO_D	Error (low active), Error pin to indicate detected error.
18	DRVOFF	HVI_D	Driver OFF (high active), secondary bridge driver disable.
19	RVSET	HVI_A	VDDIO / ADREF OV/UV configuration resister.
20	BOOST	Supply	Boost output voltage, used as supply for the gate drivers.
21	SW	PWR	Boost converter switching node connected to external coil and external diode.
22	NCS	HVI_D	SPI chip select.
23	GNDLS_B	GND	Boost GND to set current limit. Boost switching current goes through this pin through external resistor to ground.
24	EN	HVI_D	Enable (high active) of the device.
25	VDDIO	Supply	I/O supply voltage, defines the interface voltage of digital I/O, for example, SPI.
26	SCLK	HVI_D	SPI clock.
27	SDO	LVO_D	SPI data output.
28	SDI	HVI_D	SPI data input.
29	VCC3	LVO_A	VCC3 regulator, for internal use only. TI recommends an external decoupling capacitor of 0.1 µF. External load < 100 µA.
30	GNDA	GND	Analog ground.
31	RO	LVO_A	Analog output.
32	VCC5	LVO_A	VCC5 regulator, for internal use only. Recommended external decoupling capacitor 1 µF. External load < 100 µA.
33	ADREF	LVI_A	ADC reference of MCU, used as maximum voltage clamp for O1 to O3.
34	O1	LVO_A	Output current sense amplifier 1.
35	O2	LVO_A	Output current sense amplifier 2.
36	O3	LVO_A	Output current sense amplifier 3.
37	IN3	LVI_A	Current sense negative input 3.
38	IP3	LVI_A	Current sense positive input 3.
39	IN2	LVI_A	Current sense input N 2.
40	IP2	LVI_A	Current sense input P 2.
41	IN1	LVI_A	Current sense input N 1.
42	IP1	LVI_A	Current sense input P 1.
43	IHS3	HVI_D	High-side input 3, digital input to drive the HS3.
44	IHS2	HVI_D	Input HS 2, digital input to drive the HS2.
45	IHS1	HVI_D	Input HS 1, digital input to drive the HS1.
46	ILS3	HVI_D	Low-side input 3, digital input to drive the LS3.
47	ILS2	HVI_D	Input LS 2, digital input to drive the LS2.
48	ILS1	HVI_D	Input LS 1, digital input to drive the LS1.

(1) Description of pin type: GND = Ground; HVI_A = High-voltage input analog; HVI_D = High-voltage input digital; LVI_A = Low-voltage input analog; LVO_A = Low-voltage output analog; LVO_D = Low-voltage output digital; NC = No connect; PWR = Power output; Supply = Supply input

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

POS				MIN	MAX	UNIT
2.1	VS, VSH	DC voltage		–0.3	60	V
2.1a	VS	DC voltage	Negative voltages with minimum serial resistor 5 Ω, T_A = 25°C	–5		V
2.1b	VSH	DC voltage	Negative voltages with minimum serial resistor 10 Ω, T_A = 25°C	–5		V
2.1c	VS	DC voltage	Negative voltages with minimum serial resistor 5 Ω, T_A = 105°C	–2.5		V
2.1d	VSH	DC voltage	Negative voltages with minimum serial resistor 10 Ω, T_A = 105°C	–2.5		V
2.2A	GHSx	Gate high-side voltage		–9	70	V
2.2B	SHSx	Source high-side voltage		–9	70	V
2.3	GHSx-SHSx	Gate-source high-side voltage difference	Externally driven, internal limited, see position 5.4 in Electrical Characteristics	–0.3	15	V
2.4	GLSx	Gate low-side voltage		–9	20	V
2.5	SLSx	Source low-side voltage		–9	7	V
2.6	GLSx-SLSx	Gate-source low-side voltage difference	Externally driven, internal limited, see position 5.5 in Electrical Characteristics	–0.3	15	V
2.7	BOOST, SW	Boost converter		–0.3	70	V
2.8	INx, IPx	Current sense input voltage		–9	7	V
2.8A	INx, IPx	Current sense input current	Clamping current	–5	5	mA
2.8C	Ox	Current sense output voltage		–0.3	ADREF +0.3	V
2.8D	Ox	Forced input current		–10	10	mA
2.9	VDDIO	Analog input voltage		–0.3	60	V
2.9a	ADREF	Analog input voltage		–0.3	60	V
2.10	ILSx,IHSx, EN, DRVOFF, SCLK, NCS, SDI	Digital input voltage		–0.3	60	V
2.11	RVSET	Analog input voltage		–0.3	60	V
2.13	GNDA, GNDLS_B	Difference between GNDA and GNDLS_B		–0.3	0.3	V
2.20		Maximum slew rate of SHSx pins, SR_SHS		–250	250	V/µs
2.21	ERR, SDO, RO	Analog and digital output voltages		–0.3	6	V
2.21A	ERR, SDO, RO	Forced input/output current		–10	10	mA
2.22	TEST	Unused pins. Connect to GND.		–0.3	0.3	V
2.24	VCC5	Internal supply voltage		–0.3	6	V
2.24A		Short-to-ground current, I_VCC5⁽³⁾	Internal current limit		80	mA
2.25	VCC3	Internal supply voltage		–0.3	3.6	V
2.26		Short-to-ground current, I_VCC3	Limited by VCC5		80	mA
2.27		Driver FET total gate charge (per FET), Q_gmax	VS = 12 V, ƒ_PWM = 20 kHz, 6 FETs ON/OFF per PWM cycle		200⁽⁴⁾	nC
2.28		Driver FET total gate charge (per FET), Q_gmax	VS = 24 V, ƒ_PWM = 20 kHz, 6 FETs ON/OFF per PWM cycle		100⁽⁴⁾	nC
2.14		Operating virtual junction temperature, T_J		–40	150	°C
2.15		Storage temperature, T_stg		–55	165	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal, unless specified otherwise.

(3) I_VCC5 is not specifying VCC5 output current capability for external load. The allowed external load on VCC5 is specified at position 3.18 in Recommended Operating Conditions.

(4) The maximum value also depends on PCB thermal design, modulation scheme, and motor operation time.

6.2 ESD Ratings

POS					VALUE	UNIT
2.17	V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	All pins	±2000	V
2.17			Human-body model (HBM), per AEC Q100-002⁽¹⁾	Pins 4, 6, and 14	±4000
2.18			Charged-device model (CDM), per AEC Q100-011	All pins	±500
2.19			Charged-device model (CDM), per AEC Q100-011	Corner pins (1, 12, 13, 24, 25, 36, 37, and 48)	±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

POS				MIN	NOM	MAX	UNIT
3.1	VS	Supply voltage, normal voltage operation	Full device functionality. Operation at VS = 4.75 V only when coming from higher VS. Minimum VS for startup = 4.85 V	4.75		40	V
3.2	VSLO	Supply voltage, logic operation	Logic functional (during battery cranking after coming from full device functionality)	4		40	V
3.3	VDDIO	Supply voltage for digital I/Os		2.97		5.5	V
3.4	D	Duty cycle of bridge drivers		0%		100%
3.5	ƒ_PWM	PWM switching frequency		0		22⁽¹⁾	kHz
3.6A	I_VSn	VS quiescent current normal operation (boost converter enabled, drivers not switching)	Boost converter enabled, see and for SHSx/SLSx connections. EN_GDBIAS = 1			22	mA
3.61A	I_VSn	VS quiescent current normal operation (boost converter enabled, drivers not switching)	Boost converter enabled, see and for SHSx/SLSx connections. EN_GDBIAS = 0			22.3	mA
3.6B	I_BOOSTn	BOOST pin quiescent current normal operation (drivers not switching)	4.75 V < VS < 20 V, T_A = 25°C to 125°C			9	mA
3.62B	I_BOOSTn		4.75 V < VS < 20 V, T_A = –40°C			10	mA
3.61B	I_VSn	VS quiescent additional current normal operation because of RVSET thermal voltage output enabled (boost converter enabled, drivers not switching)	THERMAL_RVSET_EN = 1			0.6	mA
3.6C	I_BOOSTn	BOOST pin quiescent current normal operation (drivers not switching)	20 < VS < 40 V, T_A = 25°C to 125°C			9.5	mA
3.61C	I_BOOSTn		20 < VS < 40 V, T_A = –40°C			10.5	mA
3.6D	I_BOOST,sw	BOOST pin additional load current because of switching gate drivers	Excluding FET gate charge current. 20-kHz all gate drivers switching at the same time. EN_GDBIAS = 1			4	mA
3.61D	I_BOOST,sw	BOOST pin additional load current because of switching gate drivers	Excluding FET gate charge current. 20-kHz all gate drivers switching at the same time. EN_GDBIAS = 0			5.4	mA
3.75	I_{VSq_1}	VS quiescent current shutdown (sleep mode) 1	VS = 14 V, no operation, T_J < 25°C, EN = Low, total leakage current on all supply connected pins			20	µA
3.75a	I_{VSq_2}	VS quiescent current shutdown (sleep mode) 2	VS = 14 V, no operation, T_J < 85°C, EN = Low, total leakage current on all supply connected pins			30	µA
3.8	T_J	Junction temperature		–40		150	°C
3.9	T_A	Operating ambient free-air temperature	With proper thermal connection	–40		125	°C
3.11	V_INx,V_IPx	Current sense input voltage	V_IPx – V_Inx, RO = 2.5 V GAIN = 12	–0.15		0.15	V
3.13	ADREF	Clamping voltage for current sense amplifier outputs O1/2/3		2.97		5.5	V
3.13a		Reserved					V
3.13b		Reserved					V
3.14	VCC3	Internal supply voltage	VS > 4 V, external load current <100 µA, decoupling capacitor typical 0.1 µF	3⁽¹⁾		3.3	V
3.15	I_VCC3	VCC3 output current	Intended for MCU ADC input	0		100	µA
3.16	C_VCC3	VCC3 decoupling capacitance		0.075	0.1	0.2	µF
3.17	VCC5	Internal supply voltage	VS > 6 V, external load current < 100 µA, decoupling capacitor typical 1 µF	5.15		5.45	V
3.18	I_VCC5	VCC5 output current	Intended for MCU ADC input	0		100	µA
3.19	C_VCC5	VCC5 decoupling capacitance		0.5	1	1.5	µF

(1) Maximum PWM allowed also depends on maximum operating temperature, FET gate charge current, VS supply voltage, modulation scheme, and PCB thermal design.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV3205-Q1	UNIT
		PHP (HTQFP)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	25.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.3	°C/W
R_θJB	Junction-to-board thermal resistance	6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	5.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over operating temperature T_J = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V⁽⁴⁾, ƒ_PWM < 20 kHz (unless otherwise noted)

POS	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
4.1	CURRENT SENSE AMPLIFIER
4.2.1	V_off1a	Initial input offset of amplifiers	T_J = 25°C, ADREF = 5 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50		±1		mV
4.2.1a	V_off1a	Initial input offset of amplifiers	T_J = 25°C, ADREF = 3.3 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50		±1		mV
4.2.2	V_off1b	Temperature and aging offset⁽⁵⁾	ADREF = 5 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50		±1		mV
4.2.2a	V_off1b	Temperature and aging offset⁽⁵⁾	ADREF = 3.3 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50		±1		mV
4.2.3	V_com1⁽¹⁾	Input common voltage range		–3		3	V
4.2.4	V_Oa	Nominal output voltage level, positive ox swing	Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current	ADREF – 0.5 + V_oxm			V
4.2.4a	V_Oa	Nominal output voltage level, negative ox swing	Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current			0.5	V
4.2.4b	V_Oa	Nominal output voltage level 2, positive ox swing	Normal voltage operation, VS ≥ 5.75 V; 10-µA load current	ADREF – 0.06 + V_oxm			V
4.2.4c	V_Oa	Nominal output voltage level 2, negative ox swing	Normal voltage operation, VS ≥ 5.75 V; 10-µA load current			0.09	V
4.2.5	V_Ob	Output voltage level during low voltage operation, positive ox swing	Low voltage operation, 4.75 V ≤ VS < 5.75 V; 0.5-mA load current	VS – 1.25; ADREF – 0.5 + V_oxm			V
4.2.5a	V_Ob	Output voltage level during low voltage operation, negative ox swing	Low voltage operation, 4.75 V ≤ VS < 5.75 V; 0.5-mA load current			0.5	V
4.2.5b	V_Ob	Output voltage level during low voltage operation 2, positive ox swing	Low voltage operation, 4.75 V ≤ VS < 5.75 V; 10-µA load current	VS – 0.75; ADREF – 0.06 + V_oxm			V
4.2.5c	V_Ob	Output voltage level during low voltage operation 2, negative ox swing	Low voltage operation, 4.75 V ≤ VS < 5.75 V; 10-µA load current			0.09	V
4.2.6	GBP	Gain bandwidth product GBP	0.5 V ≤ O1/2/3 ≤ 4.5 V, capacitor load = 25 pF, specified by design.	5			MHz
4.2.8	G1	Gain 1	SPI configurable, Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current	7.896	8	8.096	V/V
4.2.9	G2	Gain 2	SPI configurable, Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current	11.856	12	12.144	V/V
4.2.10	G3	Gain 3	SPI configurable, Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current	15.808	16	16.192	V/V
4.2.11	G4	Gain 4	SPI configurable, Normal voltage operation, VS ≥ 5.75 V; 0.5-mA load current	31.616	32	32.384	V/V
4.2.12	PSRR_o123	Power supply rejection ratio at DC	VS to O1/2/3 decoupling capacitor typical 1 µF on VCC5 / 0.1-µF VCC3 at DC Specified by design, capacitor load = 25 pF RO = 2.5 V, ADREF = 5 V, gain = 16, dVS / dOx dVCC5 / dOx	60	80		dB
4.2.12a	CMRR_o123	Common mode rejection ratio at DC	Specified by design, capacitor load = 25 pF RO = 2.5 V, ADREF = 5 V, gain = 1, VS = 12 V	70	80		dB
4.2.12b	CMG_o123	Common mode gain at 500 kHz	Specified by design, capacitor load = 25 pF RO = 2.5 V, ADREF = 5 V, gain = 16			–29	dB
4.2.12c	CMG_o123	Common mode gain peak	Specified by design, capacitor load = 25 pF RO = 2.5 V, ADREF = 5 V, gain = 16			–15	dB
4.2.13	Iinamp	Inx, IPx input bias current	VCM (input common mode voltage) = ±3 V, RSHUNT_MODE[1:0] = 11		50	90	µA
4.2.13	Iinamp2	Inx, IPx input bias current	VCM (input common mode voltage) = ±3 V, RSHUNT_MODE[1:0] = 2’b000110		60	90	µA
4.2.14	Tsettle_O123	Ox settling time to withing ±2% of final value	Specified by design, capacitor load = 25 pF, RO = 2.5 V, ADREF = 5 V, gain = 16, 0.5 V ≤ O1/2/3 ≤ 4.5 V			0.8	µs
4.2.15	Iinampd	Inx, IPx Input bias differential current	VCM = ±3 V I_IPx-INx, IPx-INx = 0 V, RSHUNT_MODE[1:0] = 11	–1.2		1.2	µA
4.2.16	Rinam	Inx, IPx Input resistance	VCM = ±3 V	9	12	15	kΩ
4.2.12d	PSRR3_o123	Power supply rejection ratio at DC	VS to O1/2/3 decoupling capacitor typical 1 µF on VCC5 / 0.1-µF VCC3 at DC specified by design, capacitor load = 25 pF RO = 1.65 V ADREF = 3.3 V, gain = 16, dVS / dOx dVCC5 / dOx	70	80		dB
4.2.12e	CMRR_3o123	Common mode rejection ratio at DC	Specified by design, capacitor load = 25 pF RO = 1.65 V ADREF = 3.3 V, gain = 16 VS = 12 V	70	80		dB
4.2.12f	CMG3_o123	Common mode gain at 500 kHz	Specified by design, capacitor load = 25 pF RO = 1.65 V ADREF = 3.3 V, gain = 16			–29	dB
4.2.12g	CMG3_o123	Common mode gain peak	Specified by design, capacitor load = 25 pF RO = 1.65 V ADREF = 3.3 V, gain = 16			–15	dB
4.3	SHIFT BUFFER
4.3.2	VRO	Shift output voltage range	ADREF = 5 V	0.1 × ADREF		0.5 × ADREF	V
4.3.3	VR_offset	Shift voltage offset (with respect to RO)	ADREF = 5 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50, I_load = internal load		±1.7		mV
4.3.3a	VR_offset	Shift voltage offset (with respect to RO)	RO_CFG [4:0] = 5’b00100: ADREF × 5 / 50-5’b10111: ADREF × 24 / 50		±4		mV
4.3.3b	VR_offset	Shift voltage offset (with respect to ADREF (3.3 V) × 25 / 50 (RO_CFG [4:0] = 5'b11000))	ADREF = 3.3 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50, I_load = internal load		±1.7		mV
4.3.4	C_RO	RO output load capacitance range		0		150	pF
4.3.5	I_RO	Shift output current capability	ADREF = 5 V, RO_CFG [4:0] = 5’b11000: ADREF × 25 / 50	–5		5	mA
4.3.6	I_RO	Shift output current capability	RO_CFG [4:0] = 5’b00100: ADREF × 5 / 50-5’b10111: ADREF × 24 / 50	–1		1	mA
4.3.7	T_dgadref	ADREF UV/ OV detection deglitch time		3	5	7	µs
4.3.8	PSRR_RO	Power supply rejection ratio at DC	Decoupling capacitor typical 1 µF on VCC5 / 0.1 µF VCC3 at DC. Specified by design, capacitor load = 25 pF RO = 2.5 V ADREF = 5 V, Gain = 16, dVS / d_RO dVCC5 / d_RO	70	80		dB
4.4.9	t_dgadref	ADREF UV/OV detection deglitch time		3	5	7	µs
4.4	ADREF / VDDIO
4.4.1	V_oxm	Tolerance of ADREF voltage clamp	Relative to ADREF 5.75 V ≤ VS	–0.1	0.03	0.25	V
4.4.2	V_oxos	Overshoot of O1/2/3 over ADREF	Ox-ADREF; for <1 µs; specified by design			1.2	V
4.4.3	I_ADREF	Bias current for voltage clamping circuit	ADREF = 3.3 V, pin to ground			300	µA
4.4.4	V_ovadref	Overvoltage threshold	ADREF: 3.3-V setting by RVSET resistor	3.696	3.795	3.894	V
4.4.4a	V_ovadref	Overvoltage threshold	ADREF: 5-V setting by RVSET resistor	5.6	5.75	5.9	V
4.4.5	V_uvadref	Undervoltage threshold	ADREF: 3.3-V setting by RVSET resistor	2.706	2.805	2.904	V
4.4.5a	V_uvadref	Undervoltage threshold	ADREF: 5-V setting by RVSET resistor	4.1	4.25	4.4	V
4.4.7	V_ovvddio	Overvoltage threshold	VDDIO: 3.3-V setting by RVSET resistor	3.696	3.795	3.894	V
4.4.7a	V_ovvddio	Overvoltage threshold	VDDIO: 5-V setting by RVSET resistor	5.6	5.75	5.9	V
4.4.8	V_uvvddio	Undervoltage threshold	VDDIO: 3.3-V setting by RVSET resistor	2.706	2.805	2.904	V
4.4.8a	V_uvvddio	Undervoltage threshold	VDDIO: 5-V setting by RVSET resistor	4.1	4.25	4.4	V
4.4.10	R_vset33	VDDIO = 3.3 V / ADREF = 3.3-V mode	STAT6 bit[3:0] = 4’b0001	135	150	165	kΩ
4.4.11	R_vset53	VDDIO = 5 V / ADREF = 3.3-V mode	STAT6 bit[3:0] = 4’b0100	46	51	56.5	kΩ
4.4.12	R_vset35	VDDIO = 3.3 V / ADREF = 5-V mode	STAT6 bit[3:0] = 4’b1000	13.5	15	16.5	kΩ
4.4.13	R_vset55	VDDIO = 5 V / ADREF = 5-V mode	STAT6 bit[3:0] = 4’b0010	4.6	5.1	5.65	kΩ
4.4.30	R_vsetopen	RVSET resistor error detection		650			kΩ
4.4.31	R_vsetshort	RVSET resistor error detection				1.4	kΩ
4.4.32	V_rvsettjn40	RVSET output voltage	–40°C T_J, THERMAL_RVSET_EN = 1	1.67	1.745	1.82	V
4.4.33	V_rvsettj25		25°C T_J, THERMAL_RVSET_EN = 1	1.445	1.535	1.625
4.4.34	V_rvsettj125		125°C T_J, THERMAL_RVSET_EN = 1	1.085	1.195	1.305
	VCC3 / VCC5 REGULATORS
4.4.14	VCC3	VCC3 regulator output voltage	VS > 4 V	3	3.15	3.3	V
4.4.15	VCC3_UV	VCC3 regulator undervoltage threshold	VS > 4 V	2.7	2.85	3	V
4.4.16	VCC3_OV⁽¹⁾	VCC3 regulator overvoltage threshold	VS > 4 V	3.3	3.45	3.6	V
4.4.17	VCC5_1	VCC5 regulator output voltage 1	VS > 6 V	5.15	5.3	5.45	V
4.4.18	VCC5_2	VCC5 regulator output voltage 2	6 V > VS > 4.75 V	4.6		5.45	V
4.4.19	VCC5_UV	VCC5 regulator undervoltage threshold	VS > 4.75 V	4.3		4.6	V
4.4.20	VCC5_OV	VCC5 regulator overvoltage threshold	VS > 4.75 V	5.45	5.6	5.75	V
5.	GATE DRIVER
5.1	V_GS,low	Gate-source voltage low, high-side/low-side driver	Active pulldown, I_load = –2 mA	0		0.2	V
5.2	R_GSp	Passive gate-source resistance	Vgs ≤ 200 mV	110	220	330	kΩ
5.3	R_GSsa	Semi-active gate-source resistance	In sleep mode, V_GS > 2 V		2	4	kΩ
5.3b	I_GSL01	Low-side driver pullup/pulldown current	Gate driven low by gate driver, CURR1, 3 = 01, SPI configurable	TYP × 0.65	0.65	TYP × 1.35	A
5.3c	I_GSL00		Gate driven low by gate driver⁽¹⁾, CURR1, 3 = 00, SPI configurable	TYP × 0.1	0.15	TYP × 1.9	A
5.3d	I_GSL10		Gate driven low by gate driver, CURR1, 3 = 11, SPI configurable	TYP × 0.65	1.1	TYP × 1.35	A
5.3f	I_GSH01	High-side driver pullup/pulldown current	Gate driven low by gate driver, CURR0, 2 = 01, SPI configurable	TYP × 0.65	0.65	TYP × 1.35	A
5.3g	I_GSH00		Gate driven low by gate driver⁽¹⁾, CURR0, 2 = 00, SPI configurable	TYP × 0.1	0.15	TYP × 1.9	A
5.3h	I_GSH11		Gate driven low by gate driver, CURR0, 2 = 11, SPI configurable	TYP × 0.65	1.1	TYP × 1.35	A
5.3i	I_GSHsd	High-side/low-side driver shutdown current		2	30	70	mA
5.4	V_GS,HS,high	High-side output voltage	I_load = –2 mA; 4.75 V < VS < 40 V	9		13.4	V
5.5	V_GS,LS,high	Low-side output voltage	I_load = –2 mA	9		13.4	V
5.27	t_Don	Propagation on delay time⁽⁵⁾	After ILx/IHx rising edge, Cload = 10 nF, CURR1, 3 = 10, VGS = 1 V	100	200	350	ns
5.31	A_dt	Accuracy of dead time	If not disabled in CFG1	–15%		15%
5.32	IHSxlk_1	Source leak current, total leakage current of source pins	EN = L, SHSx = 1.5 V, T_J < 125°C	–5		5	µA
5.32a	IHSxlk_2	Source leak current, total leakage current of source pins	EN = L, SHSx = 1.5 V, 125°C < T_J < 150°C	–40		40	µA
5.29	t_Doff	Propagation off delay time⁽⁵⁾	ILx/IHx falling edge to V_GS,LS,high(V_GS,HS,high) – 1 V Ciss = 10 nF, CURR1,3 = 10,	100	200	350	ns
5.30	t_Doffdiff	Propagation off delay time difference⁽⁵⁾	LSx to LSy and HSx to HSy Cload = 10 nF, CURR1,3 = 10, V_GS,LS,high(V_GS,HS,high) – 1 V			50	ns
5.30a	t_{Don_Doff_diff}	Difference between propagation on delay time and propagation off delay time⁽⁵⁾	For each gate driver in each channel: Cload = 10 nF, CURR1, 3 = 10, VGS = 1 V (rising), V_GS,LS,high(V_GS,HS,high) – 1 V (falling)			150	ns
5.30c	t_ENoff	Propagation off (EN) deglitching time⁽⁵⁾	After falling edge on EN	2.5	6	12	µs
5.30d	t_SD	Time until gate drivers initiate shutdown⁽⁵⁾	After falling edge on EN		12	24	µs
5.30e	t_SDDRV	Time until gate drivers initiate shutdown⁽⁵⁾	After rising edge on DRVOFF			10	µs
6.	BOOST CONVERTER
6.1	V_BOOST	Boost output voltage excluding switching ripple and response delay.	BOOST-VS voltage	14	15	16.5	V
6.1b	V_BOOSTOV	Boost output voltage overvoltage with respect GND		64	67.5	70	V
6.2	I_BOOST	Output current capability	External load current including external MOSFET gate charge current BOOST – VS > V_BOOSTUV	40			mA
6.3	ƒ_BOOST	Switching frequency	BOOST – VS > V_BOOSTUV; ensured by characterization⁽³⁾	1.8	2.5	3	MHz
6.31	ƒ_BOOST	Switching frequency	BOOST – VS > V_BOOSTUV; V_S < 6 V; ensured by characterization⁽³⁾	1.1		3	MHz
6.4	V_BOOSTUV	Undervoltage shutdown level	BOOST-VS voltage	7		8	V
6.4a	V_BOOSTUV2	Undervoltage condition that device may enter RESET state	BOOST-GND voltage			10	V
6.5	t_BCSD	Filter time for undervoltage detection		5		6	µs
6.7	V_{GNDLS_B,off}	Voltage at GNDLS_B pin at which boost FET switches off because of current limit		110	150	200	mV
6.7a	t_SW,off	Delay of the GNDLS_B current limit comparator	Specified by design			100	ns
6.8	I_SW,fail	Internal second-level current limit	GNDLS_B = 0 V	840		1600	mA
6.9	R_{dson_BSTfet}	R_dson resistance boost FET	VS ≥ 6 I_SW= V_{GNDLS_B,off} / 0.33 Ω	0.25		1.5	Ω
6.9a	R_{dson_BSTfet}	R_dson resistance boost FET	VS < 6 I_SW= V_{GNDLS_B,off} / 0.33 Ω			2	Ω
7.	DIGITAL INPUTS
7.1	INL	Input low threshold	All digital inputs NCS, DRVOFF, ILSx, IHSx, SDI			VDDIO × 0.3	V
7.1a	ENH	EN input high threshold	VS > 4 V	2.7			V
7.1b	ENL	EN input low threshold	VS > 4 V			0.7	V
7.2	INH	Input high threshold	All digital inputs NCS, DRVOFF, ILSx, IHSx, SDI	VDDIO × 0.7			V
7.3	Inhys	Input hysteresis	All digital inputs EN, NCS, DRVOFF, ILSx, IHSx, SDI, VDDIO = 5 V	0.3	0.4		V
7.3a	Inhys	Input hysteresis	All digital inputs EN, NCS, DRVOFF, ILSx, IHSx, SDI, VDDIO = 3.3 V	0.2	0.3		V
7.4	R_pd,EN	Input pulldown resistor at EN pin	EN	140	200	360	kΩ
7.4a	t_deg,ENon	Power-up time after EN pin high from sleep mode to active mode	ERR = L → H			5	ms
7.5	R_pullup	Input pullup resistance	NCS, DRVOFF	200	280	400	kΩ
7.6	R_pulldown	Input pulldown resistance	ILSx, IHSx, SDI , SCLK Input voltage = 0.1 V	100	140	200	kΩ
7.6a	R_pulldown	Input pulldown current	ILSx, IHSx, SDI, SCLK Input voltage = VDDIO	4		50	µA
8.	DIGITAL OUTPUTS
8.1	OH1	Output high voltage 1	All digital outputs: SDO, I = ±2 mA; VDDIO in functional range⁽⁶⁾	VDDIO × 0.9			V
8.2	OL1	Output low voltage 1	All digital outputs: SDO, I = ±2 mA; VDDIO in functional range			VDDIO × 0.1	V
8.3	OH2	Output high voltage 2	ERR I = –0.2 mA; VDDIO in functional range	VDDIO × 0.9			V
8.4	OL2	Output low voltage 2	ERR I = +0.2 mA; VDDIO in functional range			VDDIO × 0.1	V
9.	VDS / VGS / R_SHUNT MONITORING
9.1	V_SCTH	VDS short-circuit threshold range	If not disabled in CFG1	0.1		2	V
9.2	A_vds	Accuracy of VDS monitoring	0.1-V to 0.5-V threshold setting	–50		50	mV
9.2	A_vds	Accuracy of VDS monitoring	0.6-V to 2-V threshold setting	–10%		10%
9.3	t_VDS	Detection filter time	Only rising edge of VDS comparators are filtered		5		µs
9.4	V_{gserr+_1}	VGS error detection 1	STAT7, IHSx (ILSx) = H	7		8.5	V
9.5	V_gserr–	VGS error detection	STAT7, IHSx (ILSx) = L			2	V
9.6	t_VGS	Detection filter time	CFG6[5:4]		1.0		µs
9.6a	t_VGSm	Detection mask time	CFG6[2:0]		2.5		µs
9.7	V_SHUNT	R_SHUNT shutdown threshold range	SPI configurable	75		540	mV
9.8	A_VSHUNT	Accuracy of R_SHUNT shutdown	75-mV to 165-mV setting	–18		18	mV
9.8	A_VSHUNT	Accuracy of R_SHUNT shutdown	180-mV to 540-mV setting	–10%		10%
9.9	t_VSHUNT	Detection filter time			5		µs
10.	THERMAL SHUTDOWN
10.1	T_msd0	Thermal recovery	Specified by characterization	130	153	178	°C
10.2	T_msd1	Thermal warning	Specified by characterization	140	165	190	°C
10.3	T_msd2	Thermal global reset	Specified by characterization	170	195	220	°C
10.4	T_hmsd	Thermal shutdown×2 hysteresis	Specified by characterization		40		°C
10.5	t_TSD1	Thermal warning filter time	Specified by characterization	40	45	50	µs
10.6	t_TSD2	Thermal shutdown×2 filter time	Specified by characterization	2.5	6	12	µs
12.	VS MONITORING
12.1	V_VS,OVoff0	Overvoltage shutdown level range⁽²⁾	Programmable CFG5 mode1, 12-V/24-V mode	29		38	V
12.1a	V_VS,OVoff1	Overvoltage shutdown level⁽²⁾	29-V threshold setting	27.5	29	30.5	V
12.1b	V_{VS, OVon1}	Recovery level form overvoltage shutdown⁽²⁾	29-V threshold setting	26.5	28	29.5	V
12.1c	V_VS,OVoff2	Overvoltage shutdown level⁽²⁾	33-V threshold setting	32	33.5	35	V
12.1d	V_{VS, OVon2}	Recovery level form overvoltage shutdown⁽²⁾	33-V threshold setting	31	32.5	34	V
12.1e	V_VS,OVoff3	Overvoltage shutdown level⁽²⁾	38-V threshold setting	36.5	38	39.5	V
12.1f	V_{VS, OVon3}	Recovery level form overvoltage shutdown⁽²⁾	38-V threshold setting	35.5	37	38.5	V
12.2	V_VS,UVoff	Undervoltage shutdown level⁽²⁾	VS is falling from higher voltage than 4.75 V	4.5		4.75	V
12.2a	V_VS,UVon	Recovery level form undervoltage shutdown⁽²⁾	Minimum VS for device startup	4.6		4.85	V
12.3	t_VS,SHD	Filter time for overvoltage/undervoltage shutdown		5		6	µs

(1) ADREF / VDDIO overvoltage and undervoltage is set by RVSET.

(2) Shutdown signifies predriver shutdown, not VCC3/VCC5 regulator shutdown.

(3) During startup when BOOST-VS < VBOOSTUV , ƒ_BOOST is typically 1.25 MHz.

(4) Product life time depends on VS voltage, PCB thermal design, modulation scheme, and motor operation time. The product is designed for 12-V and 24-V battery system.

(5) Ensured by characterization.

(6) All digital outputs have a push-pull output stage between VDDIO and ground.

6.6 Serial Peripheral Interface Timing Requirements

POS 13			MIN	MAX	UNIT
13.1	ƒ_SPI	SPI clock (SCLK) frequency		4⁽¹⁾	MHz
13.2	t_SPI	SPI clock period⁽²⁾	250		ns
13.3	t_high	High time: SCLK logic high duration⁽²⁾	90		ns
13.4	t_low	Low time: SCLK logic low duration⁽²⁾	90		ns
13.5	t_sucs	Setup time NCS: time between falling edge of NCS and rising edge of SCLK⁽²⁾	t_SPI / 2		ns
13.6	t_d1	Delay time: time delay from falling edge of NCS to data valid at SDO⁽²⁾		60	ns
13.7	t_susi	Setup time at SDI: setup time of SDI before the rising edge of SCLK⁽²⁾	30		ns
13.8	t_d2	Delay time: time delay from falling edge of SCLK to data valid at SDO⁽²⁾	0	60	ns
13.9	t_hcs	Hold time: time between the falling edge of SCLK and rising edge of NCS⁽²⁾	45		ns
13.10	t_hlcs	SPI transfer inactive time (time between two transfers)⁽²⁾	250		ns
13.11	t_tri	Tri-state delay time: time between rising edge of NCS and SDO in tri-state⁽²⁾		30	ns

(1) The maximum SPI clock tolerance is ±10%.

(2) Ensured by characterization.

Figure 1. SPI Timing Parameters

6.7 Typical Characteristics

Figure 2. VS Quiescent Current Shutdown

Figure 4. Propagation Delay On Time vs Temperature

Figure 3. VS Quiescent Current Shutdown

Figure 5. Propagation Delay Off Time vs Temperature

7 Detailed Description

7.1 Overview

The DRV3205-Q1 is designed to control 3-phase brushless DC motors in automotive applications using pulse-width modulation. Three high-side and three low-side gate drivers can be switched individually with low propagation delay. The input logic prevents simultaneous activation of the high-side and low-side driver of the same channel. A configuration and status register can be accessed through a SPI communication interface.

7.2 Functional Block Diagram

1. x = 1, 2, 3

2. y = 1, 2, 3

3. An external reference voltage (VCC5 or VCC3) cannot be used for ADREF voltage.

7.3 Programming

7.3.1 SPI

The SPI slave interface is used for serial communication with the external SPI master (external MCU). The SPI communication starts with the NCS falling edge and ends with NCS rising edge. The NCS high level keeps the SPI slave interface in reset state, and the SDO output in tri-state.

7.3.1.1 Address Mode Transfer

The address mode transfer is an 8-bit protocol. Both SPI slave and SPI master transmit the MSB first.

DRV3205-Q1 addr_mode_transfer_LVSCV1.gif

NOTE:

SPI master (MCU) and SPI slave (DRV3205-Q1) sample received data on the rising SCLK edge and transmit on the falling SCLK edge.

Figure 6. Single 8-Bit SPI Frame/Transfer

After the NCS falling edge, the first word of 7 bits are address bits followed by the RW bit. During first address transfer, the device returns the STAT1 register on SDO.

Each complete 8-bit frame will be processed. If NCS goes high before a multiple of 8 bits is transferred, the bits are ignored.

7.3.1.1.1 SPI Address Transfer Phase

Figure 7. SPI Address Transfer Phase Bits

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Function	ADDR6	ADDR5	ADDR4	ADDR3	ADDR2	ADDR1	ADDR0	RW

ADDR [6:0]

Read and write access

RW = 0: Read access. The SPI master performs a read access to selected register. During following SPI transfer, the device returns the requested register read value on SDO, and device interprets SDI bits as a next address transfer.

RW = 1: Write access. The master performs a write access on the selected register. The slave updates the register value during next SPI transfer (if followed immediately) and returns the current register value on SDO.

7.3.1.2 SPI Data Transfer Phase

Figure 8. SPI Data Transfer Phase Bits

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Function	DATA7	DATA6	DATA5	DATA4	ADDR3	DATA2	DATA1	DATA0

DATA [7:0]

Data value for write access (8-Bit).

Figure 8 shows data value encoding scheme during a write access. Mixing the two access modes (write and read access) during one SPI communication sequence (NCS = 0) is possible. The SPI communication can be terminated after single 8-bit SPI transfer by asserting NCS = 1. Device returns STAT1 register (for the very first SPI transfer after power-up) or current register value that was addressed during SPI Transfer Address Phase.

7.3.1.3 Device Data Response

Figure 9. Device Data Response Bits

Bit	D7	D6	D5	D4	D3	D2	D1	D0
Function	REG7	REG6	REG5	REG4	REG3	REG2	REG1	REG0

REG [7:0]

Internal register value. All unused bits are set to 0.

Figure 10 shows a complete 16-bit SPI frame. Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16 show the frame examples.

SPI Master (MCU) and SPI slave (DRV3205-Q1) sample received data on the rising SCLK edge, and transmit data on the falling SCLK edge

Figure 10. 16-Bit SPI Frame

Figure 11. Write Access Followed by Read Access

Figure 12. Read Access Followed by Read Access

Figure 13. Write Access Followed by Write Access

Figure 14. Read Access Followed by Write Access

Figure 15. Read Access Followed by Read Access Followed by Write Access

Figure 16. Read Access Followed by Read Access Followed by Read Access

7.4 Register Maps

Table 1. Register Address Map

Address	Name	Reset Value	CRC Check	Access State⁽¹⁾	Reset Event⁽²⁾ (bit wide exception)
0×01	Configuration register 0 (CFG0)	8'h3F	Yes	W/R : D, A([6:3]) R : A(7,[2:0], SF	RST1-4
0×02	Configuration register 1 (CFG1)	8'h3F	Yes	W/R: D R: A, SF	RST1-4
0×03	Configuration register 2 (CFG2)	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×04	HS 1/2/3 drive register (CURR0) ON	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×05	LS 1/2/3 drive register (CURR1) ON	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×06	HS 1/2/3 drive register (CURR2) OFF	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×07	LS 1/2/3 drive register (CURR3) OFF	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×08	Safety/error configuration register (SECR1)	8'hC0	Yes	W/R: D R: A, SF	RST1
0×09	Safety function configuration register (SFCR1)	8'h80	Yes	W/R: D R: A, SF	RST1-3
0×0A	Status register 0 (STAT0)	8'h00	No	R: D, A, SF	RST1-4
0×0B	Status register 1 (STAT1)	8'h80	No	R: D, A, SF	RST1-3
0×0C	Status register 2 (STAT2)	8'h00	No	R: D, A, SF	RST1-3
0×0D	Status register 3 (STAT3)	8'h03	No	R: D, A, SF	RST1-3
0×0E	Status register 4 (STAT4)	8'h00	No	R: D, A, SF	RST1-3
0×0F	Status register 5 (STAT5)	8'h03	No	R: D, A, SF	RST1-3 (Bit[4]:RST1)
0×10	Status register 6 (STAT6)	8'h00	No	R: D, A, SF	RST1-3
0×11	Status register 7 (STAT7)	8'h00	No	R: D, A, SF	RST1-4
0×12	Status register 8 (STAT8)	8'h00	No	R: D, A, SF	RST1-4 (Bit[0]:RST1)
0×13	Safety error status (SAFETY_ERR_STAT)	8'h00	No	R: D, A, SF	RST1-3 (Bit[3:1]:RST1)
0×14	Status register 9 (STAT9)	8'h00	No	R: D, A, SF	RST1-3
0×15	Reserved1	8'h00	No	W/R: D, A, SF	RST1-3
0×16	Reserved2	8'h00	No	W/R: D, A, SF	RST1-3
0×1E	SPI transfer write CRC register (SPIWR_CRC)	8'h00	No	W/R: D, A, SF	RST1-3
0×1F	SPI transfer read CRC register (SPIRD_CRC)	8'hFF	No	R: D, A, SF	RST1-3
0×20	SAFETY_CHECK_CTRL register ( SFCC1)	8'h01	No	W/R: D R: A, SF	RST1-3
0×21	CRC control register (CRCCTL)	8'h00	No	W/R: D, A R: SF	RST1-3
0×22	CRC calculated (CRCCALC)	N/A	No	W/R: D R: A, SF	RST1-3
0×23	Reserved 3	8'h00	No	W/R: D, A, SF	RST1-3
0×24	HS/LS read back (RB0)	8'h00	No	R: D, A, SF	RST1-3
0×25	HS/LS count control (RB1)	8'h00	No	W/R: D, A R: SF	RST1-4
0×26	HS/LS count (RB2)	8'h00	No	R: D, A, SF	RST1-4
0×27	Configuration register 3 (CFG3)	8'hAB	Yes	W/R: D R: A, SF	RST1-4
0×28	Configuration register 4 (CFG4)	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×29	Configuration register 5 (CFG5)	8'hAB	Yes	W/R: D R: A, SF	RST1-3
0×2A	CSM unlock (CSM_UNLOCK1)	8'h00	No	W/R: D R: A, SF	RST1-4
0×2B	CSM unlock (CSM_UNLOCK2)	8'h3F	No	W/R: D R: A, SF	RST1-4
0×2C	RO configuration register 2 (RO_CFG)	8'h00	Yes	W/R: D R: A, SF	RST1-4
0×2D	Safety BIST control register 1 (SAFETY_BIST_CTL1)	8'h00	Yes	W/R: D R: SF, A	RST1-3
0×2E	SPI test register (SPI_TEST)	8'h00	No	W/R: D, A, SF	RST1-4
0×2F	Reserved4	8'h00	No	W/R: D, A, SF	RST1-3
0×30	Safety BIST control register 2 (SAFETY_BIST_CTL2)	8'h00	Yes	W/R: D R: SF, A	RST1-3 (Bit[5]:RST1)
0×31	Watch dog timer configuration register (WDT_WIN1_CFG)	8'h02	Yes	W/R: D R: SF, A	RST1-4
0×32	Watch dog timer configuration register (WDT_WIN2_CFG)	8'h08	Yes	W/R: D R: SF, A	RST1-4
0×33	Watch dog timer TOKEN register (WDT_TOKEN_FDBCK)	8'h04	Yes	W/R: D R: SF, A	RST1
0×34	Watch dog timer TOKEN register (WDT_TOKEN_VALUE)	8'h40	No	R: D, SF, A	RST1-4
0×35	Watch dog timer ANSWER register (WDT_ANSWER)	8'h00	No	W/R: D, A, SF	RST1-4
0×36	Watch dog timer status register (WDT_STATUS)	8'hC0	No	R: D, A, SG	RST1-4
0×37	Watch dog failure detection configuration register (WD_FAIL_CFG)	8'hEC	Yes	W/R: D R: SF, A	RST1-4
0×38	Configuration register 6 (CFG6)	8'h10	Yes	W/R: D R: A, SF	RST1-4
0×39	Configuration register 7 (CFG7)	8'h13	Yes	W/R : D R : A, SF	RST1-4
0×3A	Configuration register 8 (CFG8)	8'h20	Yes	W/R : D R : A, SF	RST1-4
0×3B	Configuration register 9 (CFG9)	8'hFE	Yes	W/R : D R : A, SF	RST1-4

(1) W/R: Write and Read access possible, W: Write access possible, R: Read access possible
D: DIAGNOSITC STATE, A: ACTIVE STATE, SF: SAFE STATE, SY: STANDBY STATE, R: RESET

(2) RST1: Power up, RST2: System clock error detected by clock monitor RST3: VCC3 UV/OV or from other state to RESET, RST4: LBIST