The DS110DF111 is a dual-channel (1-lane bidirectional) retimer with integrated signal conditioning. The DS110DF111 includes an input Continuous-Time Linear Equalizer (CTLE), clock and data recovery (CDR), and transmit driver on each channel.
The DS110DF111 with its on-chip Decision Feedback Equalizer (DFE) can enhance the reach and robustness of long, lossy, cross-talk-impaired high speed serial links to achieve BER < 1x10-15. For less-demanding applications and interconnects, the DFE can be switched off and achieve the same BER performance. The DS125DF111 and DS110DF111 devices are pin-compatible.
Each channel of the DS110DF111 independently locks to serial data at data rates from 8.5 to 11.3 Gbps or to any supported subrate of these data rates. This simplifies system design and lowers overall cost.
Programmable transmit de-emphasis driver offers precise settings to meet the SFF-8431 output eye template. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnect and backplanes with multiple connectors. The CDR function is ideal for use in front port parallel optical module applications to reset the jitter budget and retime high-speed serial data.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DS110DF111 | WQFN (24) | 4.0 mm × 4.0 mm |
Changes from * Revision (May 2013) to A Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
HIGH SPEED DIFFERENTIAL I/OS | |||
OUTA± | 7, 8 | O, CML | Inverting and noninverting CML-compatible differential outputs. Outputs require AC coupling |
OUTB± | 20, 19 | O, CML | Inverting and noninverting CML-compatible differential outputs. Outputs require AC coupling |
INA± | 24, 23 | I, CML | Inverting and noninverting CML-compatible differential inputs. An on-chip 100 Ohm terminating resistor connects INA+ to INA- Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module. |
INB± | 11, 12 | I, CML | Inverting and noninverting CML-compatible differential inputs. An on-chip 100 Ohm terminating resistor connects INB+ to INB- Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module. |
LOOP FILTER CONNECTION PIN | |||
LPF_CP_A, LPF_REF_A | 2, 1 | I/O, analog | Loop filter connection, place a 22 nF capacitor in series between LPF_CP_A and LPF_REF_A |
LPF_CP_B, LPF_REF_B | 17, 18 | I/O, analog | Loop filter connection, place a 22 nF capacitor in series between LPF_CP_B and LPF_REF_B |
Reference Clock I/O | |||
REFCLK_IN | 14 | I, LVCMOS | 25 MHz ±100 ppm clock from external Oscillator |
INDICATOR PINS | |||
LOCK | 16 | O, LVCMOS | Goes high when CDR lock is attained on the corresponding channel. Note that this terminal is shared with strap input functions read at startup |
LOS/INT# | 13 | O, OD | Output is driven LOW when a valid signal is present on CH A. Output is released when signal on CH A is lost (LOS). This output can be redefined as an INT# signal which will be driven LOW if the EOM check returns a value below the HEO/VEO interrupt threshold(2) |
SMBus MODE PINS | |||
ENSMB | 3 | I, 4-Level | System Management Bus (SMBus) enable terminal HIGH = Register Access, SMBus Slave mode FLOAT = SMBus Master read from External EEPROM LOW = External Pin Control Mode |
SDA | 4 | I, SMBus O, OD |
Data Input / Open Drain Output External pull-up resistor is required. Terminal is 3.3 V LVCMOS tolerant(3) |
SCL | 5 | I, SMBus O, OD |
Clock input in SMBus slave mode. Can also be an open drain output in SMBus master mode Pin is 3.3 V LVCMOS Tolerant(3) |
TX_DIS | 6 | I, 4-Level | Disable the OUTB transmitter HIGH = OUTA Enabled/OUTB Disabled FLOAT = Reserved 20K to GND = Reserved LOW = OUTA/OUTB Enabled (normal operation) |
ADDR0 | 16 | I, LVCMOS | This pin sets the SMBus address for the retimer. This pin is a strap input. The state is read on power-up to set the SMBus address in SMBus control mode(3) |
ADDR1/DONE# | 10 | IO, LVCMOS | This pin sets the SMBus address for the retimer in SMBus Slave Mode. Goes low to indicate that the SMBus master EEPROM read has been completed in SMBus Master Mode(3) |
READEN# | 9 | I, 4-Level | Initiates SMBus master EEPROM read. When multiple DS110DS111 are connected to a single EEPROM, the READEN# input can be daisy chained to the DONE# output. In SMBus Slave Mode, pull low to Logic 0 proper register operation(3) |
PIN CONTROL (ENSMB = LOW)(1) | |||
DEMA | 4 | I, 4-Level | Set CHA output de-emphasis level in pin control mode(3) |
DEMB | 5 | I, 4-Level | Set CHB output de-emphasis level in pin control mode(3) |
LBK | 6 | I, 4-Level | HIGH = INA goes to OUTA, INB goes to OUTB FLOAT = INB goes to OUTA and OUTB 20K to GND = INA goes to OUTA and OUTB LOW = INA goes to OUTB, INB goes to OUTA(3) |
VODA | 9 | I, 4-Level | Set CHA output launch amplitude in pin control mode(3) |
VODB | 10 | I, 4-Level | Set CHB output launch amplitude in pin control mode(3) |
POWER | |||
VDD | 21, 22 | Power | VDD = 2.5 V ±5% 3.3 V Mode Operation: VDD Supply Output = 2.5 V ±5% 2.5 V Mode Operation: VDD Supply Input = 2.5 V ±5% |
VIN | 15 | Power | Regulator Input with Integrated Supply Mode Control 3.3 V Mode Operation: VIN Supply Input = 3.3 V ±10% 2.5 V Mode Operation: VIN Supply Input = 2.5 V ±5% |
DAP | PAD | Power | Ground reference The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package |