JAJSFW1E June   2017  – March 2019 66AK2G12

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  DSS
      2. 4.3.2  DDR EMIF
      3. 4.3.3  GPMC
      4. 4.3.4  Timers
      5. 4.3.5  I2C
      6. 4.3.6  UART
      7. 4.3.7  SPI
      8. 4.3.8  QSPI
      9. 4.3.9  McASP
      10. 4.3.10 USB
      11. 4.3.11 PCIESS
      12. 4.3.12 DCAN
      13. 4.3.13 EMAC
      14. 4.3.14 MLB
      15. 4.3.15 McBSP
      16. 4.3.16 MMC/SD
      17. 4.3.17 GPIO
      18. 4.3.18 ePWM
      19. 4.3.19 PRU-ICSS
      20. 4.3.20 Emulation and Debug Subsystem
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Boot Mode Configuration
        2. 4.3.21.2 Reset
        3. 4.3.21.3 Oscillator Reference Clocks and Clock Generator
        4. 4.3.21.4 Miscellaneous
        5. 4.3.21.5 Interrupt Controllers (INTC)
        6. 4.3.21.6 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On-Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-2  DDR3L SSTL DC Electrical Characteristics
      2. Table 5-3  I2C OPEN DRAIN DC Electrical Characteristics
      3. Table 5-4  Oscillators DC Electrical Characteristics
      4. Table 5-5  LVDS Input Buffer DC Electrical Characteristics
      5. Table 5-6  LVDS Output Buffer DC Electrical Characteristics
      6. Table 5-7  MLB LVDS Buffers DC Electrical Characteristics
      7. Table 5-8  PORn DC Electrical Characteristics
      8. Table 5-9  1.8-Volt I/O LVCMOS DC Electrical Characteristics
      9. Table 5-10 3.3-Volt I/O LVCMOS DC Electrical Characteristics
      10. 5.7.1      USB0_PHY and USB1_PHY DC Electrical Characteristics
      11. 5.7.2      PCIe SERDES DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics for ABY Package
      1. Table 5-11 Thermal Resistance Characteristics for ABY Package
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing
        1. 5.9.1.1 Power-Up Sequence
        2. 5.9.1.2 Power-Down Sequence
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Electrical Data/Timing
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1  Input Clocks / Oscillators
          1. 5.9.3.1.1 System Oscillator (SYSOSC) with External Crystal Circuit
          2. 5.9.3.1.2 System Oscillator (SYSOSC) with External LVCMOS Clock Source
          3. 5.9.3.1.3 System Oscillator (SYSOSC) Not Used
          4. 5.9.3.1.4 Optional LVDS Clock Inputs
        2. 5.9.3.2  Optional LVDS Clock Inputs Not Used
        3. 5.9.3.3  Optional Audio Oscillator (AUDOSC) with External Crystal Circuit
        4. 5.9.3.4  Optional Audio Oscillator (AUDOSC) with External LVCMOS Clock Source
        5. 5.9.3.5  Optional Audio Oscillator (AUDOSC) Not Used
        6. 5.9.3.6  Optional USB PHY Reference Clock
        7. 5.9.3.7  PCIe Reference Clock
        8. 5.9.3.8  Output Clocks
        9. 5.9.3.9  PLLs
          1. 5.9.3.9.1 DDR_PLL Settings
        10. 5.9.3.10 Recommended Clock and Control Signal Transition Behavior
      4. 5.9.4 Peripherals
        1. 5.9.4.1  DCAN
        2. 5.9.4.2  DSS
        3. 5.9.4.3  DDR EMIF
        4. 5.9.4.4  EMAC
          1. 5.9.4.4.1 EMAC MDIO Interface Timings
          2. 5.9.4.4.2 EMAC MII Timings
            1. Table 5-28 Timing Requirements for MII_RXCLK—MII Operation
            2. Table 5-29 Timing Requirements for MII_TXCLK—MII Operation
            3. Table 5-30 Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps
            4. Table 5-31 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 Mbps and 100 Mbps
          3. 5.9.4.4.3 EMAC RMII Timings
            1. Table 5-32 Timing Requirements for EMAC RMII_REFCLK—RMII Operation
            2. Table 5-33 Timing Requirements for EMAC RMII Receive
            3. Table 5-34 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK —RMII Operation
            4. Table 5-35 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 Mbps and 100 Mbps
          4. 5.9.4.4.4 EMAC RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII_RXC—RGMII Operation
            2. Table 5-37 Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps
            3. Table 5-38 Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps
            4. Table 5-39 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode
            5. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode
        5. 5.9.4.5  GPMC
          1. 5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-41 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-42 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-43 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            2. Table 5-45 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            3. Table 5-46 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        6. 5.9.4.6  I2C
          1. Table 5-47 Timing Requirements for I2C Input Timings
          2. Table 5-48 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        7. 5.9.4.7  McASP
          1. Table 5-49 Timing Requirements for McASP
        8. 5.9.4.8  McBSP
          1. Table 5-51 McBSP Timing Requirements
          2. Table 5-52 McBSP Switching Characteristics
          3. Table 5-53 McBSP Timing Requirements for FSR When GSYNC = 1
        9. 5.9.4.9  MLB
        10. 5.9.4.10 MMC/SD
          1. Table 5-60 MMC Timing Conditions
          2. Table 5-61 Timing Requirements for MMC0_CMD and MMC0_DATn
          3. Table 5-62 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode
          4. Table 5-63 Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode
          5. Table 5-64 Switching Characteristics for MMCi_CLK
          6. Table 5-65 Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0
          7. Table 5-66 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR mode
          8. Table 5-67 Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR mode
        11. 5.9.4.11 PCIESS
        12. 5.9.4.12 PRU-ICSS
          1. 5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-68 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-69 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-70 PRU-ICSS PRU Timing Requirements – Parallel Capture Mode
            3. 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-71 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-72 PRU-ICSS PRU Switching Requirements – Shift Out Mode
          2. 5.9.4.12.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-73 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              2. Table 5-74 PRU-ICSS ECAT Timing Requirements – LATCHx_IN
              3. Table 5-75 PRU-ICSS ECAT Switching Requirements – Digital IOs
          3. 5.9.4.12.3 PRU-ICSS MII_RT and Switch
            1. 5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-76 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-77 PRU-ICSS MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-78 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-79 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-80 PRU-ICSS MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-81 PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-82 PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
          4. 5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-83 PRU-ICSS UART Timing Conditions
            2. Table 5-84 Timing Requirements for PRU-ICSS UART Receive
            3. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes
            1. Table 5-86 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            2. Table 5-87 PRU-ICSS PRU Timing Requirements - EnDAT Mode
            3. Table 5-88 PRU-ICSS PRU Switching Requirements - EnDAT Mode
        13. 5.9.4.13 QSPI
        14. 5.9.4.14 SPI
          1. 5.9.4.14.1 SPI—Slave Mode
            1. Table 5-91 Timing Requirements for SPI Input Timings—Slave Mode
            2. Table 5-92 Switching Characteristics for SPI Output Timings—Slave Mode
          2. 5.9.4.14.2 SPI—Master Mode
            1. Table 5-93 SPI Timing Conditions—Master Mode
            2. Table 5-94 Timing Requirements for SPI Input Timings—Master Mode
            3. Table 5-95 Switching Characteristics for SPI Output Timings—Master Mode
        15. 5.9.4.15 Timers
        16. 5.9.4.16 UART
          1. Table 5-98 Timing Requirements for UART
          2. Table 5-99 Switching Characteristics Over Recommended Operating Conditions for UART
        17. 5.9.4.17 USB
      5. 5.9.5 Emulation and Debug Subsystem
        1. 5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.5.1.1 JTAG Electrical Data and Timing
            1. Table 5-100 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Arm A15
    4. 6.4  C66x DSP Subsystem
    5. 6.5  C66x Cache Subsystem
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 MSMC
      2. 6.7.2 DDR EMIF
      3. 6.7.3 GPMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MSGMGR
      2. 6.8.2 SEM
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  DCAN
      2. 6.10.2  DSS
      3. 6.10.3  eCAP
      4. 6.10.4  ePWM
      5. 6.10.5  eQEP
      6. 6.10.6  GPIO
      7. 6.10.7  I2C
      8. 6.10.8  ASRC
      9. 6.10.9  McASP
      10. 6.10.10 McBSP
      11. 6.10.11 MLB
      12. 6.10.12 MMC/SD
      13. 6.10.13 NSS
      14. 6.10.14 PCIESS
      15. 6.10.15 QSPI
      16. 6.10.16 SPI
      17. 6.10.17 Timers
      18. 6.10.18 UART
      19. 6.10.19 USB
  7. 7Applications, Implementation, and Layout
    1. 7.1 DDR3L Board Design and Layout Guidelines
      1. 7.1.1 DDR3L General Board Layout Guidelines
      2. 7.1.2 DDR3L Board Design and Layout Guidelines
        1. 7.1.2.1  Board Designs
        2. 7.1.2.2  DDR3L Device Combinations
        3. 7.1.2.3  DDR3L Interface Schematic
          1. 7.1.2.3.1 32-Bit DDR3L Interface
          2. 7.1.2.3.2 16-Bit DDR3L Interface
        4. 7.1.2.4  Compatible JEDEC DDR3L Devices
        5. 7.1.2.5  PCB Stackup
        6. 7.1.2.6  Placement
        7. 7.1.2.7  DDR3L Keepout Region
        8. 7.1.2.8  Bulk Bypass Capacitors
        9. 7.1.2.9  High-Speed Bypass Capacitors
          1. 7.1.2.9.1 Return Current Bypass Capacitors
        10. 7.1.2.10 Net Classes
        11. 7.1.2.11 DDR3L Signal Termination
        12. 7.1.2.12 VREF_DDR Routing
        13. 7.1.2.13 VTT
        14. 7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.1.2.14.1 Four DDR3L Devices
            1. 7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices
            2. 7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices
          2. 7.1.2.14.2 One DDR3L Device
            1. 7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device
            2. 7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device
        15. 7.1.2.15 Data Topologies and Routing Definition
          1. 7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices
          2. 7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices
        16. 7.1.2.16 Routing Specification
          1. 7.1.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 7.1.2.16.2 DQS and DQ Routing Specification
    2. 7.2 High Speed Differential Signal Routing Guidance
    3. 7.3 Power Distribution Network (PDN) Implementation Guidance
      1. 7.3.1 Decoupling/Filtering of Analog Power Supplies and Reference Inputs
        1. 7.3.1.1 PLL Power Supplies
        2. 7.3.1.2 DDR EMIF PHY DLL Power Supplies
        3. 7.3.1.3 DDR EMIF PHY Voltage Reference Input
        4. 7.3.1.4 Internal LDO Outputs
        5. 7.3.1.5 PCIe PHY Power Supply
        6. 7.3.1.6 USB PHY Power Supplies
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
    5. 7.5 Clock Routing Guidelines
      1. 7.5.1 Oscillator Routing
      2. 7.5.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Receiving Notification of Documentation Updates
      1. 8.4.1 静電気放電に関する注意事項
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABY|625
サーマルパッド・メカニカル・データ
発注情報

Table 5-43 GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)

NO. PARAMETER MIN MAX UNIT
F0 1 / tc(clk) Frequency(18), output clock GPMC_CLK 100 MHz
F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high 0.5P(15) 0.5P(15) ns
F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low 0.5P(15) 0.5P(15) ns
tdc(clk) Duty cycle error, output clock GPMC_CLK -500 500 ps
tJ(clk) Jitter standard deviation(19), output clock GPMC_CLK 33.33 ps
tR(clk) Rise time, output clock GPMC_CLK 2 ns
tF(clk) Fall time, output clock GPMC_CLK 2 ns
tR(do) Rise time, output data GPMC_AD[15:0] 2 ns
tF(do) Fall time, output data GPMC_AD[15:0] 2 ns
F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x](14) transition F(6) - 2.2 F(6) + 4.5 ns
F3 td(clkH-csnIV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x](14) invalid E(5) - 2.2 E(5) + 4.5 ns
F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge B(2) - 4.5 B(2) + 3.1 ns
F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid -2.3 4.5 ns
F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge B(2) - 1.9 B(2) + 2.3 ns
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11) D(4) - 2.3 D(4) + 1.9 ns
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) D(4) - 2.3 D(4) + 1.9 ns
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13) D(4) - 2.3 D(4) + 1.9 ns
F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition G(7) - 2.3 G(7) + 4.5 ns
F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid D(4) - 2.3 D(4) + 4.5 ns
F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition H(8) - 2.3 H(8) + 3.5 ns
F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid H(8) - 2.3 H(8) + 3.5 ns
F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition I(9) - 2.3 I(9) + 4.5 ns
F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11) J(10) - 2.3 J(10) + 2.7 ns
F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) J(10) - 2.3 J(10) + 2.7 ns
F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13) J(10) - 2.3 J(10) + 2.7 ns
F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11) J(10) - 2.3 J(10) + 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) J(10) - 2.3 J(10) + 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13) J(10) - 2.3 J(10) + 1.9 ns
F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[x](14) low Read A(1) ns
Write A(1) ns
F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C(3) ns
Write C(3) ns
F20 tw(advnV) Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low Read K(16) ns
Write K(16) ns
  1. For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    With n being the page burst access number.
  2. B = ClkActivationTime × GPMC_FCLK(17)
  3. For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    With n being the page burst access number.
  4. For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  5. For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  6. For csn falling edge (CS activated):
    • Case GpmcFCLKDivider = 0:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
      • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
      • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
      • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
  7. For ADV falling edge (ADV activated):
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

    For ADV rising edge (ADV deactivated) in Reading mode:
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

    For ADV rising edge (ADV deactivated) in Writing mode:
    • Case GpmcFCLKDivider = 0:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
      • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
      • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
  8. For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
    • Case GpmcFCLKDivider = 0:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
      • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

    For OE rising edge (OE deactivated):
    • Case GpmcFCLKDivider = 0:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
      • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
      • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
  9. For WE falling edge (WE activated):
    • Case GpmcFCLKDivider = 0:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
    • Case GpmcFCLKDivider = 1:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
      • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

    For WE rising edge (WE deactivated):
    • Case GpmcFCLKDivider = 0:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
    • Case GpmcFCLKDivider = 1:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
    • Case GpmcFCLKDivider = 2:
      • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
      • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
      • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
  10. J = GPMC_FCLK(17)
  11. First transfer only for CLK DIV 1 mode.
  12. Half cycle; for all data after initial transfer for CLK DIV 1 mode.
  13. Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
  14. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
  15. P = GPMC_CLK period in ns
  16. For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
    For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
  17. GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
  18. Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
  19. The jitter probability density can be approximated by a Gaussian function.
66AK2G12 gpmc1_sprs717.gif
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-36 GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)AB
66AK2G12 gpmc2_sprs717.gif
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-37 GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)AB
66AK2G12 gpmc3_sprs717.gif
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-38 GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)AB
66AK2G12 gpmc4_sprs717.gif
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-39 GPMC and Multiplexed NOR Flash—Synchronous Burst ReadAB
66AK2G12 gpmc5_sprs717.gif
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-40 GPMC and Multiplexed NOR Flash—Synchronous Burst WriteAB