JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | MIN | MAX | UNIT | |
---|---|---|---|---|
FI1 | Delay time, output data GPMC_AD[15:0] generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI2 | Delay time, input data GPMC_AD[15:0] capture from internal functional clock GPMC_FCLK(3) | 4 | ns | |
FI3 | Delay time, output chip select GPMC_CSn[x] generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI4 | Delay time, output address GPMC_A[27:1] generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI5 | Delay time, output address GPMC_A[27:1] valid from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI6 | Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI7 | Delay time, output enable GPMC_OEn_REn generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI8 | Delay time, output write enable GPMC_WEn generation from internal functional clock GPMC_FCLK(3) | 6.5 | ns | |
FI9 | Skew, internal functional clock GPMC_FCLK(3) | 100 | ps |