JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
tR(d) | Rise time, output data GPMC_AD[15:0] | 2 | ns | |||
tF(d) | Fall time, output data GPMC_AD[15:0] | 2 | ns | |||
FA0 | tw(be[x]nV) | Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time | Read | N(12) | ns | |
Write | N(12) | |||||
FA1 | tw(csnV) | Pulse duration, output chip select GPMC_CSn[x](13) low | Read | A(1) | ns | |
Write | A(1) | |||||
FA3 | td(csnV-advnIV) | Delay time, output chip select GPMC_CSn[x](13) valid to output address valid and address latch enable GPMC_ADVn_ALE invalid | Read | B(2) - 0.2 | B(2) + 2.0 | ns |
Write | B(2) - 0.2 | B(2) + 2.0 | ||||
FA4 | td(csnV-oenIV) | Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn invalid (Single read) | C(3) - 0.2 | C(3) + 2.0 | ns | |
FA9 | td(aV-csnV) | Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[x](13) valid | J(9) - 0.2 | J(9) + 2.0 | ns | |
FA10 | td(be[x]nV-csnV) | Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[x](13) valid | J(9) - 0.2 | J(9) + 2.0 | ns | |
FA12 | td(csnV-advnV) | Delay time, output chip select GPMC_CSn[x](13) valid to output address valid and address latch enable GPMC_ADVn_ALE valid | K(10) - 0.2 | K(10) + 2.0 | ns | |
FA13 | td(csnV-oenV) | Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn valid | L(11) - 0.2 | L(11) + 2.0 | ns | |
FA16 | tw(aIV) | Pulse durationm output address GPMC_A[26:1] invalid between 2 successive read and write accesses | G(7) | ns | ||
FA18 | td(csnV-oenIV) | Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn invalid (Burst read) | I(8) - 0.2 | I(8) + 2.0 | ns | |
FA20 | tw(aV) | Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses | D(4) | ns | ||
FA25 | td(csnV-wenV) | Delay time, output chip select GPMC_CSn[x](13) valid to output write enable GPMC_WEn valid | E(5) - 0.2 | E(5) + 2.0 | ns | |
FA27 | td(csnV-wenIV) | Delay time, output chip select GPMC_CSn[x](13) valid to output write enable GPMC_WEn invalid | F(6) - 0.2 | F(6) + 2.0 | ns | |
FA28 | td(wenV-dV) | Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid | 2.8 | ns | ||
FA29 | td(dV-csnV) | Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[x](13) valid | J(9) - 0.2 | J(9) + 2.8 | ns | |
FA37 | td(oenV-aIV) | Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end | 2.8 | ns |
For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory Subsystem of the Device TRM.