JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | PARAMETER | STANDARD MODE | FAST MODE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
I15 | tc(SCL) | Cycle time, SCL | 10 | 2.5 | µs | ||
I16 | tsu(SCLH-SDAL) | Setup Time, SCL high before SDA low (for a repeated START condition) | 4.7 | 0.6 | µs | ||
I17 | th(SDAL-SCLL) | Hold time, SCL low after SDA low (for a START and a repeated START condition) | 4 | 0.6 | µs | ||
I18 | tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | µs | ||
I19 | tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | µs | ||
I20 | tsu(SDAV-SCLH) | Setup time, SDA valid before SCL high | 250 | 100 | ns | ||
I21 | th(SCLL-SDAV) | Hold time, SDA valid after SCL low | 0 | 3.45 | 0 | 0.9 | µs |
I22 | tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | µs | ||
I23 | tr(SDA) | Rise time, SDA | 1000 | 20 + 0.1Cb(1) | 300 | ns | |
I24 | tr(SCL) | Rise time, SCL | 1000 | 20 + 0.1Cb(1) | 300 | ns | |
I25 | tf(SDA) | Fall time, SDA | 300 | 20 + 0.1Cb(1) | 300 | ns | |
I26 | tf(SCL) | Fall time, SCL | 300 | 20 + 0.1Cb(1) | 300 | ns | |
I27 | tsu(SCLH-SDAH) | Setup time, high before SDA high (for STOP condition) | 4 | 0.6 | µs |
NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of driving high when transmitting logic-1.
For more information, see section Inter-IC module (I2C) in chapter Peripherals of the Device TRM.