JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
SIGNAL NAME [1] | DESCRIPTION [2] | PIN TYPE [3] | ABY BALL [4] |
---|---|---|---|
DDR3_A00 | EMIF address bit 00 output | OZ | AC15 |
DDR3_A01 | EMIF address bit 01 output | OZ | Y15 |
DDR3_A02 | EMIF address bit 02 output | OZ | AC16 |
DDR3_A03 | EMIF address bit 03 output | OZ | AA15 |
DDR3_A04 | EMIF address bit 04 output | OZ | AB16 |
DDR3_A05 | EMIF address bit 05 output | OZ | AE17 |
DDR3_A06 | EMIF address bit 06 output | OZ | AC14 |
DDR3_A07 | EMIF address bit 07 output | OZ | AB15 |
DDR3_A08 | EMIF address bit 08 output | OZ | AC17 |
DDR3_A09 | EMIF address bit 09 output | OZ | AB17 |
DDR3_A10 | EMIF address bit 10 output | OZ | AB14 |
DDR3_A11 | EMIF address bit 11 output | OZ | AA16 |
DDR3_A12 | EMIF address bit 12 output | OZ | AA17 |
DDR3_A13 | EMIF address bit 13 output | OZ | AA12 |
DDR3_A14 | EMIF address bit 14 output | OZ | Y17 |
DDR3_A15 | EMIF address bit 15 output | OZ | Y16 |
DDR3_BA0 | EMIF bank address 0 output | OZ | AA14 |
DDR3_BA1 | EMIF bank address 1 output | OZ | AB13 |
DDR3_BA2 | EMIF bank address 2 output | OZ | AD17 |
DDR3_CASn | EMIF column address strobe output | OZ | AC13 |
DDR3_CB00 | EMIF ECC check bit 00 input/output | IOZ | AA11 |
DDR3_CB01 | EMIF ECC check bit 01 input/output | IOZ | AB11 |
DDR3_CB02 | EMIF ECC check bit 02 input/output | IOZ | AC11 |
DDR3_CB03 | EMIF ECC check bit 03 input/output | IOZ | AC12 |
DDR3_CBDQM | EMIF ECC check bits data mask output | OZ | Y11 |
DDR3_CBDQS_N | EMIF ECC check bit data strobe input/output (negative) | IOZ | AD12 |
DDR3_CBDQS_P | EMIF ECC check bit data strobe input/output (positive) | IOZ | AE12 |
DDR3_CEn0 | EMIF chip enable 0 output (Active Low) | OZ | AD13 |
DDR3_CKE0 | EMIF clock enable 0 output | OZ | AB18 |
DDR3_CLKOUT_N0 | EMIF differential clock 0 output (negative) | OZ | AD15 |
DDR3_CLKOUT_P0 | EMIF differential clock 0 output (positive) | OZ | AE15 |
DDR3_CLKOUT_N1 | EMIF differential clock 1 output (negative) | OZ | AD16 |
DDR3_CLKOUT_P1 | EMIF differential clock 1 output (positive) | OZ | AE16 |
DDR3_D00 | EMIF data bit 00 input/output | IOZ | AD2 |
DDR3_D01 | EMIF data bit 01 input/output | IOZ | Y4 |
DDR3_D02 | EMIF data bit 02 input/output | IOZ | AC3 |
DDR3_D03 | EMIF data bit 03 input/output | IOZ | AC2 |
DDR3_D04 | EMIF data bit 04 input/output | IOZ | AE3 |
DDR3_D05 | EMIF data bit 05 input/output | IOZ | AA4 |
DDR3_D06 | EMIF data bit 06 input/output | IOZ | AD3 |
DDR3_D07 | EMIF data bit 07 input/output | IOZ | AB3 |
DDR3_D08 | EMIF data bit 08 input/output | IOZ | AA6 |
DDR3_D09 | EMIF data bit 09 input/output | IOZ | Y7 |
DDR3_D10 | EMIF data bit 10 input/output | IOZ | Y6 |
DDR3_D11 | EMIF data bit 11 input/output | IOZ | AC5 |
DDR3_D12 | EMIF data bit 12 input/output | IOZ | AB6 |
DDR3_D13 | EMIF data bit 13 input/output | IOZ | Y5 |
DDR3_D14 | EMIF data bit 14 input/output | IOZ | AC4 |
DDR3_D15 | EMIF data bit 15 input/output | IOZ | AB5 |
DDR3_D16 | EMIF data bit 16 input/output | IOZ | AB7 |
DDR3_D17 | EMIF data bit 17 input/output | IOZ | AB8 |
DDR3_D18 | EMIF data bit 18 input/output | IOZ | AC7 |
DDR3_D19 | EMIF data bit 19 input/output | IOZ | AA7 |
DDR3_D20 | EMIF data bit 20 input/output | IOZ | AA8 |
DDR3_D21 | EMIF data bit 21 input/output | IOZ | AC6 |
DDR3_D22 | EMIF data bit 22 input/output | IOZ | AE7 |
DDR3_D23 | EMIF data bit 23 input/output | IOZ | AD7 |
DDR3_D24 | EMIF data bit 24 input/output | IOZ | AA10 |
DDR3_D25 | EMIF data bit 25 input/output | IOZ | AE10 |
DDR3_D26 | EMIF data bit 26 input/output | IOZ | AD10 |
DDR3_D27 | EMIF data bit 27 input/output | IOZ | AC10 |
DDR3_D28 | EMIF data bit 28 input/output | IOZ | AC9 |
DDR3_D29 | EMIF data bit 29 input/output | IOZ | AB10 |
DDR3_D30 | EMIF data bit 30 input/output | IOZ | AB9 |
DDR3_D31 | EMIF data bit 31 input/output | IOZ | Y8 |
DDR3_DQM0 | EMIF data mask 0 output for byte 0 of the 32-bit data bus | OZ | AB4 |
DDR3_DQM1 | EMIF data mask 1 output for byte 1 of the 32-bit data bus | OZ | AA5 |
DDR3_DQM2 | EMIF data mask 2 output for byte 2 of the 32-bit data bus | OZ | AC8 |
DDR3_DQM3 | EMIF data mask 3 output for byte 3 of the 32-bit data bus | OZ | AA9 |
DDR3_DQS0_N | EMIF differential data strobe 0 negative input/output for byte 0 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AE2 |
DDR3_DQS0_P | EMIF differential data strobe 0 positive input/output for byte 0 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AD1 |
DDR3_DQS1_N | EMIF differential data strobe 1 negative input/output for byte 1 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AE4 |
DDR3_DQS1_P | EMIF differential data strobe 1 positive input/output for byte 1 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AD4 |
DDR3_DQS2_N | EMIF differential data strobe 2 negative input/output for byte 2 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AD6 |
DDR3_DQS2_P | EMIF differential data strobe 2 positive input/output for byte 2 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AE6 |
DDR3_DQS3_N | EMIF differential data strobe 3 negative input/output for byte 3 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AD9 |
DDR3_DQS3_P | EMIF differential data strobe 3 positive input/output for byte 3 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. | IOZ | AE9 |
DDR3_ODT0 | EMIF on-die termination output for chip select 0 | OZ | AA13 |
DDR3_RASn | EMIF row address strobe output | OZ | AE13 |
DDR3_RESETn | EMIF reset output (DDR3L-SDRAM only) | OZ | Y18 |
DDR3_RZQ0 | EMIF calibration resistor. An external 240 Ω ±1% resistor must be connected between this pin and VSS. | A | W12 |
DDR3_RZQ1 | EMIF calibration resistor. An external 240 Ω ±1% resistor must be connected between this pin and VSS. | A | V9 |
DDR3_WEn | EMIF write enable output | OZ | Y13 |
DDR_CLK_N | EMIF DPLL differential reference clock input (Negative) | I | AD24 |
DDR_CLK_P | EMIF DPLL differential reference clock input (Positive) | I | AE24 |
For more information, see section DDR Extrenal Memory Interface (EMIF) in chapter Memory Subsystem of the Device TRM.