JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Transmit Timing | |||||
U1 | tw(TXSTART) | Pulse width, transmit start bit | U(1) - 2 | U(1) + 2 | ns |
U2 | tw(TXH) | Pulse width, transmit data/parity bit high | U(1) - 2 | U(1) + 2 | ns |
tw(TXL) | Pulse width, transmit data/parity bit low | U(1) - 2 | U(1) + 2 | ns | |
U3 | tw(TXSTOP1) | Pulse width, transmit stop bit 1 | U(1) - 2 | U(1) + 2 | ns |
tw(TXSTOP15) | Pulse width, transmit stop bit 1.5 | 1.5U(1) - 2 | 1.5U(1) + 2 | ns | |
tw(TXSTOP2) | Pulse width, transmit stop bit 2 | 2U(1) - 2 | 2U(1) + 2 | ns | |
Autoflow Timing Requirements | |||||
U7 | td(RX-RTSH) | Delay time, STOP bit received to RTS deasserted | P(2) | 5P(2) | ns |
U8 | td(CTSL-TX) | Delay time, CTS asserted to START bit transmit | P(2) | 5P(2) | ns |
For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the Device TRM.