JAJSFW1E June 2017 – March 2019 66AK2G12
PRODUCTION DATA.
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There are two internal LDOs that require external decoupling capacitors.
The LDO_PCIE_CAP pins are connected to the output of an internal LDO that sources the PCIe PHY core power rail. A single 1.0 µF, ±50% decoupling capacitor with ESR of 10–100 mΩ must be connected between the LDO_PCIE_CAP pins and VSS with less than 0.5 nH of loop inductance.
The LDO_USB_CAP pins are connected to the output of an internal LDO that sources both USB PHY core power rails. A single 1.0 µF, ±50% decoupling capacitor with ESR of 10–100 mΩ must be connected between the LDO_USB_CAP pins and VSS with less than 0.5 nH of loop inductance.