JAJSN14
October 2021
ADC09DJ800
,
ADC09QJ800
,
ADC09SJ800
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
概要 (続き)
5
Revision History
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: DC Specifications
7.6
Electrical Characteristics: Power Consumption
7.7
Electrical Characteristics: AC Specifications
7.8
Timing Requirements
7.9
Switching Characteristics
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Device Comparison
8.3.2
Analog Input
8.3.2.1
Analog Input Protection
8.3.2.2
Full-Scale Voltage (VFS) Adjustment
8.3.2.3
Analog Input Offset Adjust
8.3.2.4
ADC Core
8.3.2.4.1
ADC Theory of Operation
8.3.2.4.2
ADC Core Calibration
8.3.2.4.3
Analog Reference Voltage
8.3.2.4.4
ADC Over-range Detection
8.3.2.4.5
Code Error Rate (CER)
8.3.3
Temperature Monitoring Diode
8.3.4
Timestamp
8.3.5
Clocking
8.3.5.1
Converter PLL (C-PLL) for Sampling Clock Generation
8.3.5.2
LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
8.3.5.3
Optional CMOS Clock Outputs (ORC, ORD)
8.3.5.4
SYSREF for JESD204C Subclass-1 Deterministic Latency
8.3.5.4.1
SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
8.3.5.4.2
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
8.3.6
JESD204C Interface
8.3.6.1
Transport Layer
8.3.6.2
Scrambler
8.3.6.3
Link Layer
8.3.6.4
8B/10B Link Layer
8.3.6.4.1
Data Encoding (8B/10B)
8.3.6.4.2
Multiframes and the Local Multiframe Clock (LMFC)
8.3.6.4.3
Code Group Synchronization (CGS)
8.3.6.4.4
Initial Lane Alignment Sequence (ILAS)
8.3.6.4.5
Frame and Multiframe Monitoring
8.3.6.5
64B/66B Link Layer
8.3.6.5.1
64B/66B Encoding
8.3.6.5.2
Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
8.3.6.5.2.1
Block, Multiblock and Extended Multiblock Alignment using Sync Header
8.3.6.5.2.1.1
Cyclic Redundancy Check (CRC) Mode
8.3.6.5.2.1.2
Forward Error Correction (FEC) Mode
8.3.6.5.3
Initial Lane Alignment
8.3.6.5.4
Block, Multiblock and Extended Multiblock Alignment Monitoring
8.3.6.6
Physical Layer
8.3.6.6.1
SerDes Pre-Emphasis
8.3.6.7
JESD204C Enable
8.3.6.8
Multi-Device Synchronization and Deterministic Latency
8.3.6.9
Operation in Subclass 0 Systems
8.3.6.10
Alarm Monitoring
8.3.6.10.1
Clock Upset Detection
8.3.6.10.2
FIFO Upset Detection
8.4
Device Functional Modes
8.4.1
Low Power Mode and High Performance Mode
8.4.2
JESD204C Modes
8.4.2.1
JESD204C Transport Layer Data Formats
8.4.2.2
64B/66B Sync Header Stream Configuration
8.4.2.3
Redundant Data Mode (Alternate Lanes)
8.4.3
Power-Down Modes
8.4.4
Test Modes
8.4.4.1
Serializer Test-Mode Details
8.4.4.2
PRBS Test Modes
8.4.4.3
Clock Pattern Mode
8.4.4.4
Ramp Test Mode
8.4.4.5
Short and Long Transport Test Mode
8.4.4.5.1
Short Transport Test Pattern
8.4.4.6
D21.5 Test Mode
8.4.4.7
K28.5 Test Mode
8.4.4.8
Repeated ILA Test Mode
8.4.4.9
Modified RPAT Test Mode
8.4.5
Calibration Modes and Trimming
8.4.5.1
Foreground Calibration Mode
8.4.5.2
Background Calibration Mode
8.4.5.3
Low-Power Background Calibration (LPBG) Mode
8.4.6
Offset Calibration
8.4.7
Trimming
8.5
Programming
8.5.1
Using the Serial Interface
8.5.2
SCS
8.5.3
SCLK
8.5.4
SDI
8.5.5
SDO
8.5.6
Streaming Mode
8.5.7
SPI_Register_Map Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Light Detection and Ranging (LiDAR) Digitizer
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Analog Front-End Requirements
9.2.1.2.2
Calculating Clock and SerDes Frequencies
9.2.1.3
Application Curves
9.3
Initialization Set Up
10
Power Supply Recommendations
10.1
Power Sequencing
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
AAV|144
MPBGAM2C
サーマルパッド・メカニカル・データ
発注情報
jajsn14_oa
7
Specifications