JAJSMJ1A march 2023 – may 2023 ADC12DJ5200SE
PRODUCTION DATA
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ADC12DJ5200SE can operate with subclass 0 compatibility provided that multi-ADC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as normal to initiate the CGS and ILAS in 8B/10B mode.