JAJSMJ1B March   2023  – June 2024 ADC12DJ5200SE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Comparison
      2. 6.3.2  Analog Inputs
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3  ADC Core
        1. 6.3.3.1 ADC Theory of Operation
        2. 6.3.3.2 ADC Core Calibration
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Overrange Detection
        5. 6.3.3.5 Code Error Rate (CER)
      4. 6.3.4  Temperature Monitoring Diode
      5. 6.3.5  Timestamp
      6. 6.3.6  Clocking
        1. 6.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.6.3.2 Automatic SYSREF Calibration
      7. 6.3.7  Programmable FIR Filter (PFIR)
        1. 6.3.7.1 Dual Channel Equalization
        2. 6.3.7.2 Single Channel Equalization
        3. 6.3.7.3 Time Varying Filter
      8. 6.3.8  Digital Down Converters (DDC)
        1. 6.3.8.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.8.1.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.8.1.2 NCO Selection
          3. 6.3.8.1.3 Basic NCO Frequency Setting Mode
          4. 6.3.8.1.4 Rational NCO Frequency Setting Mode
          5. 6.3.8.1.5 NCO Phase Offset Setting
          6. 6.3.8.1.6 52
          7. 6.3.8.1.7 NCO Phase Synchronization
        2. 6.3.8.2 Decimation Filters
        3. 6.3.8.3 Output Data Format
        4. 6.3.8.4 Decimation Settings
          1. 6.3.8.4.1 Decimation Factor
          2. 6.3.8.4.2 DDC Gain Boost
      9. 6.3.9  JESD204C Interface
        1. 6.3.9.1 Transport Layer
        2. 6.3.9.2 Scrambler
        3. 6.3.9.3 Link Layer
        4. 6.3.9.4 8B/10B Link Layer
          1. 6.3.9.4.1 Data Encoding (8B/10B)
          2. 6.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.9.4.3 Code Group Synchronization (CGS)
          4. 6.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.9.4.5 Frame and Multiframe Monitoring
        5. 6.3.9.5 64B/66B Link Layer
          1. 6.3.9.5.1 64B/66B Encoding
          2. 6.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 6.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 6.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 6.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 6.3.9.5.4 Initial Lane Alignment
          5. 6.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.9.6 Physical Layer
          1. 6.3.9.6.1 SerDes Pre-Emphasis
        7. 6.3.9.7 JESD204C Enable
        8. 6.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 6.3.9.9 Operation in Subclass 0 Systems
      10. 6.3.10 Alarm Monitoring
        1. 6.3.10.1 NCO Upset Detection
        2. 6.3.10.2 Clock Upset Detection
        3. 6.3.10.3 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 6.4.4 JESD204C Modes
        1. 6.4.4.1 JESD204C Operating Modes Table
        2. 6.4.4.2 JESD204C Modes cont.
        3. 6.4.4.3 JESD204C Transport Layer Data Formats
        4. 6.4.4.4 64B/66B Sync Header Stream Configuration
        5. 6.4.4.5 Dual DDC and Redundant Data Mode
      5. 6.4.5 Power-Down Modes
      6. 6.4.6 Test Modes
        1. 6.4.6.1 Serializer Test-Mode Details
        2. 6.4.6.2 PRBS Test Modes
        3. 6.4.6.3 Clock Pattern Mode
        4. 6.4.6.4 Ramp Test Mode
        5. 6.4.6.5 Short and Long Transport Test Mode
          1. 6.4.6.5.1 Short Transport Test Pattern
          2. 6.4.6.5.2 Long Transport Test Pattern
        6. 6.4.6.6 D21.5 Test Mode
        7. 6.4.6.7 K28.5 Test Mode
        8. 6.4.6.8 Repeated ILA Test Mode
        9. 6.4.6.9 Modified RPAT Test Mode
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
        2. 6.4.7.2 Background Calibration Mode
        3. 6.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 SPI Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband RF Sampling Receiver
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.4.3 JESD204C Transport Layer Data Formats

Output data are formatted in a specific optimized fashion for each JMODE setting based on the transport layer settings for that JMODE. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into octets. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 6-26. In all mappings, the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.

Table 6-26 JMODE Table Symbol Definitions
NOTATIONMODEDESCRIPTION
S[n]Single channel, DDC bypassedSample n from ADC in single channel mode when DDC is bypassed
A[n]Dual channel, DDC bypassedSample n from channel A in dual channel mode when DDC is bypassed
B[n]Dual channel, DDC bypassedSample n from channel A in dual channel mode when DDC is bypassed
T—Tail bits, always set to 0
AI[n], AQ[n]Dual channel, DDC enabledComplex I/Q sample n from DDC A in dual channel mode
BI[n], BQ[n]Dual channel, DDC enabledComplex I/Q sample n from DDC B in dual channel mode
ORA0[n]Dual channel, DDC enabledOverrange flag for channel A, set high if channel A sample n exceeds overrange threshold 0 (OVR_T0)
ORA1[n]Dual channel, DDC enabledOverrange flag for channel A, set high if channel A sample n exceeds overrange threshold 1 (OVR_T1)
ORB0[n]Dual channel, DDC enabledOverrange flag for channel B, set high if channel B sample n exceeds overrange threshold 0 (OVR_T0)
ORB1[n]Dual channel, DDC enabledOverrange flag for channel B, set high if channel B sample n exceeds overrange threshold 1 (OVR_T1)
I[n], Q[n]Single channel, DDC enabledComplex I/Q sample n from the DDC in single channel mode
OR0[n]Single channel, DDC enabledOverrange flag, set high if sample n exceeds overrange threshold 0 (OVR_T0)
OR1[n]Single channel, DDC enabledOverrange flag, set high if sample n exceeds overrange threshold 1 (OVR_T1)
Table 6-27 JMODES 0 an d 30 (12-bit, Single Channel, DDC Bypass, 8 lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S[0]S[8]S[16]S[24]S[32]T
DA1S[2]S[10]S[18]S[26]S[34]T
DA2S[4]S[12]S[20]S[28]S[36]T
DA3S[6]S[14]S[22]S[30]S[38]T
DB0S[1]S[9]S[17]S[25]S[33]T
DB1S[3]S[11]S[19]S[27]S[35]T
DB2S[5]S[13]S[21]S[29]S[37]T
DB3S[7]S[15]S[23]S[31]S[39]T
Table 6-28 JMODES 1 and 40 (12-bit, Single Channel, DDC Bypass, 16 lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S[0]S[16]S[32]S[48]S[64]T
DA1S[2]S[18]S[34]S[50]S[66]T
DA2S[4]S[20]S[36]S[52]S[68]T
DA3S[6]S[22]S[38]S[54]S[70]T
DA4S[8]S[24]S[40]S[56]S[72]T
DA5S[10]S[26]S[42]S[58]S[74]T
DA6S[12]S[28]S[44]S[60]S[76]T
DA7S[14]S[30]S[46]S[62]S[78]T
DB0S[1]S[17]S[33]S[49]S[65]T
DB1S[3]S[19]S[35]S[51]S[67]T
DB2S[5]S[21]S[37]S[53]S[69]T
DB3S[7]S[23]S[39]S[55]S[71]T
DB4S[9]S[25]S[41]S[57]S[73]T
DB5S[11]S[27]S[43]S[59]S[75]T
DB6S[13]S[29]S[45]S[61]S[77]T
DB7S[15]S[31]S[47]S[63]S[79]T
Table 6-29 JMODES 2 and 31 (12-Bit, Dual Channel, DDC Bypass, 8 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A[0]A[4]A[8]A[12]A[16]T
DA1A[1]A[5]A[9]A[13]A[17]T
DA2A[2]A[6]A[10]A[14]A[18]T
DA3A[3]A[7]A[11]A[15]A[19]T
DB0B[0]B[4]B[8]B[12]B[16]T
DB1B[1]B[5]B[9]B[13]B[17]T
DB2B[2]B[6]B[10]B[14]B[18]T
DB3B[3]B[7]B[11]B[15]B[19]T
Table 6-30 JMODES 3 and 41 (12-Bit, Dual Channel, DDC Bypass, 16 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A[0]A[8]A[16]A[24]A[32]T
DA1A[1]A[9]A[17]A[25]A[33]T
DA2A[2]A[10]A[18]A[26]A[34]T
DA3A[3]A[11]A[19]A[27]A[35]T
DA4A[4]A[12]A[20]A[28]A[36]T
DA5A[5]A[13]A[21]A[29]A[37]T
DA6A[6]A[14]A[22]A[30]A[38]T
DA7A[7]A[15]A[23]A[31]A[39]T
DB0B[0]B[8]B[16]B[24]B[32]T
DB1B[1]B[9]B[17]B[25]B[33]T
DB2B[2]B[10]B[18]B[26]B[34]T
DB3B[3]B[11]B[19]B[27]B[35]T
DB4B[4]B[12]B[20]B[28]B[36]T
DB5B[5]B[13]B[21]B[29]B[37]T
DB6B[6]B[14]B[22]B[30]B[38]T
DB7B[7]B[15]B[23]B[31]B[39]T
Table 6-31 JMODES 5 and 44 (8-bit, Single Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DA2S[4]
DA3S[6]
DB0S[1]
DB1S[3]
DB2S[5]
DB3S[7]
Table 6-32 JMODES 6 and 50 (8-bit, Single Channel, 16 Lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DA2S[4]
DA3S[6]
DA4S[8]
DA5S[10]
DA6S[12]
DA7S[14]
DB0S[1]
DB1S[3]
DB2S[5]
DB3S[7]
DB4S[9]
DB5S[11]
DB6S[13]
DB7S[15]
Table 6-33 JMODES 7 and 45 (8-bit, Dual Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DA2A[2]
DA3A[3]
DB0B[0]
DB1B[1]
DB2B[2]
DB3B[3]
Table 6-34 JMODES 8 and 51 (8-bit, Dual Channel, 16 Lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DA2A[2]
DA3A[3]
DA4A[4]
DA5A[5]
DA6A[6]
DA7A[7]
DB0B[0]
DB1B[1]
DB2B[2]
DB3B[3]
DB4B[4]
DB5B[5]
DB6B[6]
DB7B[7]
Table 6-35 JMODES 10 and 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]
Table 6-36 JMODES 11 and 47 (15-bit, Dual Channel, Decimate-by-4, 8 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AQ[0], ORA1[0]
DA3AQ[1], ORA1[1]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BQ[0], ORB1[0]
DB3BQ[1], ORB1[1]
Table 6-37 JMODES 12 and 53 (15-bit, Dual Channel, Decimate-by-4, 16 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AI[2], ORA0[2]
DA3AI[3], ORA0[3]
DA4AQ[0], ORA1[0]
DA5AQ[1], ORA1[1]
DA6AQ[2], ORA1[2]
DA7AQ[3], ORA1[3]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BI[2], ORB0[2]
DB3BI[3], ORB0[3]
DB4BQ[0], ORB1[0]
DB5BQ[1], ORB1[1]
DB6BQ[2], ORB1[2]
DB7BQ[3], ORB1[3]
Table 6-38 JMODES 13, 39, 56, 59, 66, and 68 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]
Table 6-39 JMODES 14, 49, 57, 60, and 67 (15-bit, Dual Channel, Decimate-by-8, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]
Table 6-40 JMODES 15, 55, and 58 (15-bit, Dual Channel, Decimate-by-8, 8 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AQ[0], ORA1[0]
DA3AQ[1], ORA1[1]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BQ[0], ORB1[0]
DB3BQ[1], ORB1[1]
Table 6-41 JMODE 16 (15-bit, Dual Channel, Decimate-by-8, 16 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AI[1], ORA0[1]
DA2AI[2], ORA0[2]
DA3AI[3], ORA0[3]
DA4AQ[0], ORA1[0]
DA5AQ[1], ORA1[1]
DA6AQ[2], ORA1[2]
DA7AQ[3], ORA1[3]
DB0BI[0], ORB0[0]
DB1BI[1], ORB0[1]
DB2BI[2], ORB0[2]
DB3BI[3], ORB0[3]
DB4BQ[0], ORB1[0]
DB5BQ[1], ORB1[1]
DB6BQ[2], ORB1[2]
DB7BQ[3], ORB1[3]
Table 6-42 JMODES 19 and 42 (12-bit, Single Channel, DDC Bypass, 12 lanes)
OCTET01
NIBBLE0123
DA0S[0][11:0]S[2][11:8]
DA1S[2][7:0]S[4][11:4]
DA2S[4][3:0]S[6][11:0]
DA3S[8][11:0]S[10][11:8]
DA4S[10][7:0]S[12][11:4]
DA5S[12][3:0]S[14][11:0]
DB0S[1][11:0]S[3][11:8]
DB1S[3][7:0]S[5][11:4]
DB2S[5][3:0]S[7][11:0]
DB3S[9][11:0]S[11][11:8]
DB4S[11][7:0]S[13][11:4]
DB5S[13][3:0]S[15][11:0]
Table 6-43 JMODE 20 and 43 (12-bit, Dual Channel, DDC Bypass, 12 lanes)
OCTET01
NIBBLE0123
DA0A[0][11:0]A[1][11:8]
DA1A[1][7:0]A[2][11:4]
DA2A[2][3:0]A[3][11:0]
DA3A[4][11:0]A[5][11:8]
DA4A[5][7:0]A[6][11:4]
DA5A[6][3:0]A[7][11:0]
DB0B[0][11:0]B[1][11:8]
DB1B[1][7:0]B[2][11:4]
DB2B[2][3:0]B[3][11:0]
DB3B[4][11:0]B[5][11:8]
DB4B[5][7:0]B[6][11:4]
DB5B[6][3:0]B[7][11:0]
Table 6-44 JMODE 21 and 36 (15-bit, Single Channel, Decimate-by-4, 4 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
Table 6-45 JMODES 22 and 46 (15-bit, Single Channel, Decimate-by-4, 8 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]
Table 6-46 JMODES 23, 38, 61, 64, 69, and 71 (15-bit, Single Channel, Decimate-by-8, 2 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DB0Q[0], OR1[0]
Table 6-47 JMODES 24, 48, 62, 65, and 70 (15-bit, Single Channel, Decimate-by-8, 4 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
Table 6-48 JMODES 25 and 52 (15-bit, Single Channel, Decimate-by-4, 16 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[0]
DA2I[2], OR0[1]
DA3I[3], OR0[1]
DA4I[4], OR0[2]
DA5I[5], OR0[2]
DA6I[6], OR0[3]
DA7I[7], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[0]
DB2Q[2], OR1[1]
DB3Q[3], OR1[1]
DB4Q[4], OR1[2]
DB5Q[5], OR1[2]
DB6Q[6], OR1[3]
DB7Q[7], OR1[3]
Table 6-49 JMODE 26, 54, and 63 (15-bit, Single Channel, Decimate-by-8, 8 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]
Table 6-50 JMODE 27 (15-bit, Single Channel, Decimate-by-8, 16 lanes)
OCTET01
NIBBLE0123
DA0I[0], OR0[0]
DA1I[1], OR0[1]
DA2I[2], OR0[2]
DA3I[3], OR0[3]
DA4I[4], OR0[4]
DA5I[5], OR0[5]
DA6I[6], OR0[6]
DA7I[7], OR0[7]
DB0Q[0], OR1[0]
DB1Q[1], OR1[1]
DB2Q[2], OR1[2]
DB3Q[3], OR1[3]
DB4Q[4], OR1[4]
DB5Q[5], OR1[5]
DB6Q[6], OR1[6]
DB7Q[7], OR1[7]
Table 6-51 JMODE 32 (12-bit, Single Channel, DDC Bypass, 6 lanes)
OCTET01
NIBBLE0123
DA0S[0][11:0]S[2][11:8]
DA1S[2][7:0]S[4][11:4]
DA2S[4][3:0]S[6][11:0]
DB0S[1][11:0]S[3][11:8]
DB1S[3][7:0]S[5][11:4]
DB2S[5][3:0]S[7][11:0]
Table 6-52 JMODE 33 (12-bit, Dual Channel, DDC Bypass, 6 lanes)
OCTET01
NIBBLE0123
DA0A[0][11:0]A[1][11:8]
DA1A[1][7:0]A[2][11:4]
DA2A[2][3:0]A[3][11:0]
DB0B[0][11:0]B[1][11:8]
DB1B[1][7:0]B[2][11:4]
DB2B[2][3:0]B[3][11:0]
Table 6-53 JMODE 34 (8-bit, Single Channel, 4 lanes)
OCTET0
NIBBLE01
DA0S[0]
DA1S[2]
DB0S[1]
DB1S[3]
Table 6-54 JMODE 35 (8-bit, Dual Channel, 4 lanes)
OCTET0
NIBBLE01
DA0A[0]
DA1A[1]
DB0B[0]
DB1B[1]
Table 6-55 JMODE 37 (15-bit, Dual Channel, Decimate-by-4, 4 lanes)
OCTET01
NIBBLE0123
DA0AI[0], ORA0[0]
DA1AQ[0], ORA1[0]
DB0BI[0], ORB0[0]
DB1BQ[0], ORB1[0]
Table 6-56 JMODE 38 (15-bit, Single Channel, Decimate-by-8, 2 lanes)
OCTET0
NIBBLE01
DA0I[0], OR0[0]
DB0Q[0], OR1[0]
Table 6-57 JMODE 39 (15-bit, Dual Channel, Decimate-by-8, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]
Table 6-58 JMODE 56 (15-bit, Dual Channel, Decimate-by-16, 2 lanes)
OCTET0123
NIBBLE01234567
DA0AI[0], ORA0[0]AQ[0], ORA1[0]
DB0BI[0], ORB0[0]BQ[0], ORB1[0]