JAJSSY9 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.15 Typical Characteristics - ADC12DL2500 (2GSPS)

Typical values are at TA = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347MHz, AIN = –1dBFS, fCLK = 2GHz, filtered 1VPP sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM) and foreground calibration; SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and signal-independent interleaving spurs (fS / 4 and fS / 2 spurs)

GUID-20240123-SS0I-2RHH-DNRL-HFPXMXDLGX77-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration
Figure 5-180 SNR vs Input Frequency
GUID-20240123-SS0I-5GJG-HDXH-K3QQRB9MK89N-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration
Figure 5-182 SINAD vs Input Frequency
GUID-20240123-SS0I-LZRJ-6CJJ-M5HGGWSZSMFS-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration
Figure 5-184 ENOB vs Input Frequency
GUID-20240123-SS0I-TCCL-NR1S-TRSKJLWQRW8G-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration
Figure 5-186 SFDR vs Input Frequency
GUID-20240123-SS0I-V9TM-W4NN-KWLFN2XW0CRN-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration
Figure 5-188 HD2 and HD3 vs Input Frequency
GUID-20240123-SS0I-DF7L-QVNB-NG4B2QP2L1DJ-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, includes fS / 2 – fIN spur only
Figure 5-190 Worst Interleaving Spur vs Input Frequency
GUID-20240125-SS0I-RT6T-X1BX-GL1QBSSGMS6P-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, SNR = 57.3dBFS, SFDR = 70.6dBFS, ENOB = 9.1 bits
Figure 5-192 Single-Tone FFT at fIN = 99MHz, AIN = –1dBFS
GUID-20240125-SS0I-TFPC-6CKB-RTDQBMWTFSDM-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, SNR = 57.3dBFS, SFDR = 66.4dBFS, ENOB = 9.0 bits
Figure 5-194 Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
GUID-20240125-SS0I-M3JK-KMF6-K8FWNFJ5XGK0-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, SNR = 57.0dBFS, SFDR = 68.5dBFS, ENOB = 9.1 bits
Figure 5-196 Single-Tone FFT at fIN = 797MHz, AIN = –1dBFS
GUID-20240125-SS0I-9LFF-PBTH-ZDGSLTB1DRC7-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, SNR = 56.2dBFS, SFDR = 61.8dBFS, ENOB = 8.6 bits
Figure 5-198 Single-Tone FFT at fIN = 2488MHz, AIN = –1dBFS
GUID-20240126-SS0I-4T03-ZV3L-BLLLF6BTZ3HW-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, f1 = 89MHz, f2 = 99MHz, AIN = -7dBFS per tone, SFDR = -71dBFS, IMD3 = -94dBFS, IMD2 = -77dBFS
Figure 5-200 Two-Tone FFT at fIN = 94MHz, AIN = –1dBFS
GUID-20240126-SS0I-8NR0-NQB4-2QNJMGLZZ1ZT-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, f1 = 342MHz, f2 = 352MHz, AIN = -7dBFS per tone, SFDR = -69dBFS, IMD3 = -95dBFS, IMD2 = -77dBFS
Figure 5-202 Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
GUID-20240126-SS0I-7ZDV-09TD-87KPHQWPVJNN-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, f1 = 792MHz, f2 = 802MHz, AIN = -7dBFS per tone, SFDR = -65dBFS, IMD3 = -87dBFS, IMD2 = -74dBFS
Figure 5-204 Two-Tone FFT at fIN = 797MHz, AIN = –1dBFS
GUID-20240126-SS0I-CKGM-R0X4-RMRQ6N6GCTTN-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, FIN = 99MHz
Figure 5-206 DNL vs Code
GUID-20240126-SS0I-5VD5-4HFK-NMC5ZSJ191LQ-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, FIN = 99MHz
Figure 5-208 DNL vs Code
GUID-20240123-SS0I-SZQH-SFSM-6PMCML5BM2H2-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration
Figure 5-181 SNR vs Input Frequency
GUID-20240123-SS0I-LVKG-HQKS-DPBM1KMKTXW3-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration
Figure 5-183 SINAD vs Input Frequency
GUID-20240123-SS0I-TNF4-M6XJ-MRJFQ4M1CNCF-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration
Figure 5-185 ENOB vs Input Frequency
GUID-20240123-SS0I-HV0D-MP4X-5NXJXQNV7Z24-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration
Figure 5-187 SFDR vs Input Frequency
GUID-20240123-SS0I-QBG6-09X6-RJ7MCR2LQBTP-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration
Figure 5-189 HD2 and HD3 vs Input Frequency
GUID-20240123-SS0I-VMGJ-BXHZ-0XCRRXMZCJFP-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, includes fS / 2 – fIN and fS /4 ± fIN spurs only
Figure 5-191 Worst Interleaving Spur vs Input Frequency
GUID-20240125-SS0I-GSBB-J2VW-CGXHCWL6HNDJ-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, SNR = 57.3dBFS, SFDR = 64.4dBFS, ENOB = 9.0 bits
Figure 5-193 Single-Tone FFT at fIN = 99MHz, AIN = –1dBFS
GUID-20240125-SS0I-8DMW-4DV3-D1B2PXSNJJS5-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, SNR = 56.9dBFS, SFDR = 62.7dBFS, ENOB = 8.9 bits
Figure 5-195 Single-Tone FFT at fIN = 347MHz, AIN = –1dBFS
GUID-20240125-SS0I-CQBC-JCBF-TTHSCDF8FP2Z-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, SNR = 57.1dBFS, SFDR = 61.7dBFS, ENOB = 8.8 bits
Figure 5-197 Single-Tone FFT at fIN = 797MHz, AIN = –1dBFS
GUID-20240126-SS0I-HFHP-91MN-VDTLDXLKB58G-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, f1 = 89MHz, f2 = 99MHz, AIN = -7dBFS per tone, SFDR = -75dBFS, IMD3 = -95dBFS, IMD2 = -90dBFS
Figure 5-199 Two-Tone FFT at fIN = 94MHz, AIN = –1dBFS
GUID-20240126-SS0I-Z2FH-CMW1-TZ6V6F1GKLWB-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, f1 = 342MHz, f2 = 352MHz, AIN = -7dBFS per tone, SFDR = -75dBFS, IMD3 = -79dBFS, IMD2 = -75dBFS
Figure 5-201 Two-Tone FFT at fIN = 347MHz, AIN = –1dBFS
GUID-20240126-SS0I-LJRC-BHRM-K7CVC8QS8WZ9-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, f1 = 792MHz, f2 = 802MHz, AIN = -7dBFS per tone, SFDR = -76dBFS, IMD3 = -88dBFS, IMD2 = -81dBFS
Figure 5-203 Two-Tone FFT at fIN = 797MHz, AIN = –1dBFS
GUID-20240126-SS0I-CL3W-FMCX-9WGL4SGWQ9LW-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, f1 = 2483MHz, f2 = 2493MHz, AIN = -7dBFS per tone, SFDR = -65dBFS, IMD3 = -73dBFS, IMD2 = -73dBFS
Figure 5-205 Two-Tone FFT at fIN = 2488MHz, AIN = –1dBFS
GUID-20240126-SS0I-CQDZ-TVSP-FLFRNHDP6STQ-low.svg
DES_EN = 0, fS = 2000MHz, FG calibration, FIN = 99MHz
Figure 5-207 INL vs Code
GUID-20240126-SS0I-HBXP-G22Z-6Z4JLPJQ8B3W-low.svg
DES_EN = 1, fS = 4000MHz, FG calibration, FIN = 99MHz
Figure 5-209 INL vs Code