JAJSSY9 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

Typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 0, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration; minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommending Operating Conditions table.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC12DL500
FPBW Full-power input bandwidth (–3 dB)(1) Foreground calibration 8.0 GHz
XTALK Channel-to-channel crosstalk Aggressor = 400 MHz, –1 dBFS -94 dB
CER Code error rate Maximum CER 10-18 errors/ sample
NSD Noise spectral density, no input signal Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting -143.5 dBFS/Hz
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting -142.3
NF Noise figure Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω 31.5 dB
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω 30.7
NOISEDC DC input noise standard deviation No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) 1.8 LSB
SNR Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –1 dBFS 56.8 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 57.6
fIN = 347 MHz, AIN = –1 dBFS 56.7
SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –16 dBFS 57.3 dBFS
fIN = 347 MHz, AIN = –16 dBFS 57.4
SINAD Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 56 dBFS
fIN = 347 MHz, AIN = –1 dBFS 55.9
ENOB Effective number of bits, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 9.0 bits
fIN = 347 MHz, AIN = –1 dBFS 9.0
SFDR Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 69 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 65
fIN = 347 MHz, AIN = –1 dBFS 67
SFDR Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –16 dBFS 75 dBFS
fIN = 347 MHz, AIN = –16 dBFS 72
FS/2 FS/2 fixed interleaving spur, independent of input signal No input -71 dBFS
HD2 2nd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -75 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -72
fIN = 347 MHz, AIN = –1 dBFS -67
HD3 3rd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -71 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -67
fIN = 347 MHz, AIN = –1 dBFS -69
FS/2-FIN FS/2-FIN interleaving spur, signal dependent fIN = 97 MHz, AIN = –1 dBFS -77 dBFS
fIN = 347 MHz, AIN = –1 dBFS -71
SPUR Worst harmonic 4th-order or higher fIN = 97 MHz, AIN = –1 dBFS -72 dBFS
fIN = 347 MHz, AIN = –1 dBFS -71
IMD3 3rd-order intermodulation fIN = 97 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -82 dBFS
fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -80
ADC12DL1500
FPBW Full-power input bandwidth (–3 dB)(1) Foreground calibration 8.0 GHz
XTALK Channel-to-channel crosstalk Aggressor = 400 MHz, –1 dBFS -93 dB
Aggressor = 1000 MHz, –1 dBFS -80
CER Code error rate Maximum CER 10-18 errors/ sample
NSD Noise spectral density, no input signal Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting -148.0 dBFS/Hz
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting -146.7
NF Noise figure Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω 27.0 dB
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω 26.3
NOISEDC DC input noise standard deviation No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) 1.9 LSB
SNR Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –1 dBFS 56.6 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 57.3
fIN = 347 MHz, AIN = –1 dBFS 56.7
fIN = 797 MHz, AIN = –1 dBFS 56.5
SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –16 dBFS 57 dBFS
fIN = 347 MHz, AIN = –16 dBFS 56.9
fIN = 797 MHz, AIN = –16 dBFS 57.1
SINAD Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 55.7 dBFS
fIN = 347 MHz, AIN = –1 dBFS 56.3
fIN = 797 MHz, AIN = –1 dBFS 55.8
ENOB Effective number of bits, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 9.0 bits
fIN = 347 MHz, AIN = –1 dBFS 9.1
fIN = 797 MHz, AIN = –1 dBFS 9.0
SFDR Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 67 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 65
fIN = 347 MHz, AIN = –1 dBFS 65
fIN = 797 MHz, AIN = –1 dBFS 62
SFDR Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –16 dBFS 72 dBFS
fIN = 347 MHz, AIN = –16 dBFS 72
fIN = 797 MHz, AIN = –16 dBFS 73
FS/2 FS/2 fixed interleaving spur, independent of input signal No input -74 dBFS
HD2 2nd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -71 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -71
fIN = 347 MHz, AIN = –1 dBFS -71
fIN = 797 MHz, AIN = –1 dBFS -65
HD3 3rd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -68 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -66
fIN = 347 MHz, AIN = –1 dBFS -69
fIN = 797 MHz, AIN = –1 dBFS -69
FS/2-FIN FS/2-FIN interleaving spur, signal dependent fIN = 97 MHz, AIN = –1 dBFS -74 dBFS
fIN = 347 MHz, AIN = –1 dBFS -73
fIN = 797 MHz, AIN = –1 dBFS -73
SPUR Worst harmonic 4th-order or higher fIN = 97 MHz, AIN = –1 dBFS -72 dBFS
fIN = 347 MHz, AIN = –1 dBFS -70
fIN = 797 MHz, AIN = –1 dBFS -70
IMD3 3rd-order intermodulation fIN = 97 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -87 dBFS
fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -85
fIN = 797 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -83
ADC12DL2500
FPBW Full-power input bandwidth (–3 dB)(1) Foreground calibration 8.0 GHz
XTALK Channel-to-channel crosstalk Aggressor = 400 MHz, –1 dBFS -83 dB
Aggressor = 1000 MHz, –1 dBFS -76
Aggressor = 3000 MHz, –1 dBFS -59
CER Code error rate Maximum CER 10-18 errors/ sample
NSD Noise spectral density, no input signal Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting -149.8 dBFS/Hz
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting -148.3
NF Noise figure Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, no input, ZS = 100 Ω 25.2 dB
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, no input, ZS = 100 Ω 24.7
NOISEDC DC input noise standard deviation No input, excludes DC offset, includes fixed interleaving spur (FS/2 spur) 2.0 LSB
SNR Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –1 dBFS 56.3 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 57
fIN = 347 MHz, AIN = –1 dBFS 56.1
fIN = 797 MHz, AIN = –1 dBFS 56
fIN = 2397 MHz, AIN = –1 dBFS 54.6
fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 55.1
SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 97 MHz, AIN = –16 dBFS 56.8 dBFS
fIN = 347 MHz, AIN = –16 dBFS 56.5
fIN = 797 MHz, AIN = –16 dBFS 56.7
fIN = 2397 MHz, AIN = –16 dBFS 56.7
SINAD Signal-to-noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 55.9 dBFS
fIN = 347 MHz, AIN = –1 dBFS 55.7
fIN = 797 MHz, AIN = –1 dBFS 54.6
fIN = 2397 MHz, AIN = –1 dBFS 53.2
ENOB Effective number of bits, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 9.0 bits
fIN = 347 MHz, AIN = –1 dBFS 9.0
fIN = 797 MHz, AIN = –1 dBFS 8.8
fIN = 2397 MHz, AIN = –1 dBFS 8.5
SFDR Spurious-free dynamic range, large signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –1 dBFS 65 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 65
fIN = 347 MHz, AIN = –1 dBFS 66
fIN = 797 MHz, AIN = –1 dBFS 64
fIN = 2397 MHz, AIN = –1 dBFS 60
fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting 56
SFDR Spurious-free dynamic range, small signal, excluding DC and FS/2 fixed spurs fIN = 97 MHz, AIN = –16 dBFS 74 dBFS
fIN = 347 MHz, AIN = –16 dBFS 72
fIN = 797 MHz, AIN = –16 dBFS 72
fIN = 2397 MHz, AIN = –16 dBFS 73
FS/2 FS/2 fixed interleaving spur, independent of input signal No input -75 dBFS
HD2 2nd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -76 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -71
fIN = 347 MHz, AIN = –1 dBFS -73
fIN = 797 MHz, AIN = –1 dBFS -68
fIN = 2397 MHz, AIN = –1 dBFS -62
fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -59
HD3 3rd-order harmonic fIN = 97 MHz, AIN = –1 dBFS -68 dBFS
fIN = 97 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -66
fIN = 347 MHz, AIN = –1 dBFS -68
fIN = 797 MHz, AIN = –1 dBFS -65
fIN = 2397 MHz, AIN = –1 dBFS -63
fIN = 2397 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting -58
FS/2-FIN FS/2-FIN interleaving spur, signal dependent fIN = 97 MHz, AIN = –1 dBFS -72 dBFS
fIN = 347 MHz, AIN = –1 dBFS -72
fIN = 797 MHz, AIN = –1 dBFS -74
fIN = 2397 MHz, AIN = –1 dBFS -68
SPUR Worst harmonic 4th-order or higher fIN = 97 MHz, AIN = –1 dBFS -71 dBFS
fIN = 347 MHz, AIN = –1 dBFS -70
fIN = 797 MHz, AIN = –1 dBFS -69
fIN = 2397 MHz, AIN = –1 dBFS -69
IMD3 3rd-order intermodulation fIN = 97 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -80 dBFS
fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -79
fIN = 797 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -83
fIN = 2397 MHz ± 5 MHz,
AIN = –7 dBFS per tone		 -69
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.