JAJSSY9 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10 Switching Characteristics

typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), foreground calibration; minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tAD Sampling (aperture) delay from CLK± rising edge (dual channel mode) or rising and falling edge (single channel mode) to sampling instant(4) TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 360 ps
tAD(MAX) Maximum tAD Adjust programmable delay, not including clock inversion (TAD_INV = 0) Coarse adjustment (TAD_COARSE = 0xFF) 289 ps
Fine adjustment (TAD_FINE = 0xFF) 4.9
tAD(STEP) Aperture delay step size Coarse adjustment (TAD_COARSE) 1.13 ps
Fine adjustment (TAD_FINE) 19 fs
tAJ Aperture jitter, rms Minimum tAD Adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 55 fs
Minimum tAD Adjust coarse setting (TAD_COARSE = 0xFF, TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 70
Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 70(1)
Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 80(1)
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±)
fBIT Output bit rate per output data pair 1.6 Gbps
fDCLK DDR data clock frequency 800 MHz
tDJ DDR data clock total jitter, peak-to-peak, with random jitter portion defined with respect to a BER=1e–15 (Q=7.94) UPAT_CTRL = 0x10 36 ps
tSKEW(SAME) Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) within the same LVDS bank over operating conditions 75 ps
tSKEW(ALL) Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) in all LVDS banks over operating conditions with tOSAB, tOSAC and tOSBD skew excluded 125 ps
tOSAB Functional timing offset between DACLK± rising edge and DBCLK± rising edge, positive number indicates that DACLK± leads DBCLK± DES_EN = 0, LDEMUX = 0, LALIGNED = 0 0 tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 1 0
DES_EN = 0, LDEMUX = 1, LALIGNED = 0 0
DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0
DES_EN = 1, LDEMUX = 0, LALIGNED = 0 0.5
DES_EN = 1, LDEMUX = 0, LALIGNED = 1 0
DES_EN = 1, LDEMUX = 1, LALIGNED = 0 0.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0
tOSAC Functional timing offset between DACLK± rising edge and DCCLK± rising edge, positive number indicates that DACLK± leads DCCLK± DES_EN = 0, LDEMUX = 1, LALIGNED = 0 1 tCLK
DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0
DES_EN = 1, LDEMUX = 1, LALIGNED = 0 1
DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0
tOSBD Functional timing offset between DBCLK± rising edge and DDCLK± rising edge, positive number indicates that DBCLK± leads DDCLK± DES_EN = 0, LDEMUX = 1, LALIGNED = 0 1 tCLK
DES_EN = 0, LDEMUX = 1, LALIGNED = 1 0
DES_EN = 1, LDEMUX = 1, LALIGNED = 0 1
DES_EN = 1, LDEMUX = 1, LALIGNED = 1 0
tTLH Low-to-high transition time (differential) 20% to 80%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 125 ps
20% to 80%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 200
tTHL High-to-low transition time (differential) 80% to 20%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10 125 ps
80% to 20%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10 200
LATENCY
tOD Output delay from CLK± rising edge (dual-channel mode) or falling edge (single-channel mode) to DACLK± output(4) TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0 1.5 ns
tLAT(DIG) CLK± edge that samples input signal to CLK± edge that launches data, digital latency only(2)(4) DES_EN = 0, LDEMUX = 0, LALIGNED = 0 26 tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 1 26
DES_EN = 0, LDEMUX = 1, LALIGNED = 0 26
DES_EN = 0, LDEMUX = 1, LALIGNED = 1 27
DES_EN = 1, LDEMUX = 0, LALIGNED = 0 26
DES_EN = 1, LDEMUX = 0, LALIGNED = 1 26.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 0 26
DES_EN = 1, LDEMUX = 1, LALIGNED = 1 27.5
tLAT(STB) Latency from SYSREF± being sampled by rising edge of CLK± to the start of the corresponding data frame(3) DES_EN = 0, LDEMUX = 0, LALIGNED = 0 47 tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 1 47
DES_EN = 0, LDEMUX = 1, LALIGNED = 0 47
DES_EN = 0, LDEMUX = 1, LALIGNED = 1 48
DES_EN = 1, LDEMUX = 0, LALIGNED = 0 46.5
DES_EN = 1, LDEMUX = 0, LALIGNED = 1 47
DES_EN = 1, LDEMUX = 1, LALIGNED = 0 46.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 1 48
tLAT(SYNCSE) Latency from SYNCSE assertion or deassertion to DB0± (LSB) changing from normal data to strobe output or strobe output to normal data, digital latency only LDEMUX = 0 26 36+1*LFRAME tCLK
LDEMUX = 1 26 36+2*LFRAME
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD) Delay from falling edge of 16th SCLK cycle during read operation for SDO transition from tri-state to valid data 1 ns
t(ODZ) Delay from SCS rising edge for SDO to transition from valid data to tri-state 10 ns
t(OD) Delay from falling edge of SCLK during read operation to SDO valid 1 10 ns
(1) tAJ increases because of additional attenuation on internal clock path.
(2) When LDEMUX = 1 the output buses are aligned in time requiring the earlier sample(s) to be delayed before outputting on the LVDS buses to align with the later samples. The latency for the buses will be slightly different due to added delays. The number shown is for the worst case bus.
(3) When LDEMUX = 0 the output buses are staggered in time and therefore the start of data frames occur at staggered times. The number shown is for the earliest output frame. The strobe signals are output at the end of a frame so the start of a data frame corresponds to the data output immediately after a strobe output.
(4) Both tAD and tOD increase by the delay introduced by TAD_COARSE, TAD_FINE and TAD_INV when tAD Adjust is used to delay the sampling instant. The total latency through the device does not include the aperture delay. Total latency through device is tLAT = tLAT(DIG) + tOD - tAD.