JAJSFG3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.5.5 Scrambling

The LVDS outputs can be scrambled in order to reduce spectral peaks in the output data, especially for repeating patterns. Spectral peaks can couple back to the ADC analog input and result in degraded noise or spurious performance in the ADC output data. Enable scrambling by setting SCR in the LCTRL register. The scrambler does not require any memory (only uses the current sample) and uses simple XOR operations in order to minimize latency. Scrambling does require the two LSBs of each sample to be random (as is the case for ADC input thermal noise), but also works when the LSB is used as a strobe or timestamp. The scrambler is enabled by setting SCR in the LCTRL register to 1. The scrambling operation changes slightly depending on the LWIDTH parameter, as Table 7-12 to Table 7-15 describes. Each table also describes the descrambling operation that the receiving device must implement in order to recover the original samples. In Table 7-12 to Table 7-15, d[x] corresponds to bit x of the unscrambled digitized ADC sample at LVDS bus q (q = A, B, C, or D) before scrambling and y[k] corresponds to the scrambled bit k output from the interface over data pair Dqk±. Likewise, strobe is the unscrambled strobe signal at the LVDS bus q (q = A, B, C, or D) and strobe_y is the scrambled strobe output on data pair DqSTR±. The ⊕ symbol denotes the bitwise XOR operation.

Table 7-12 Scrambling and Descrambling Operations (12-Bit Mode, LWIDTH = 0x0)
SCRAMBLERDESCRAMBLER
y[11] = d[11] ⊕ d[1] ⊕ d[0]d[11] = y[11] ⊕ y[0]
y[10] = d[10] ⊕ d[1] ⊕ d[0]d[10] = y[10] ⊕ y[0]
y[9] = d[9] ⊕ d[1] ⊕ d[0]d[9] = y[9] ⊕ y[0]
y[8] = d[8] ⊕ d[1] ⊕ d[0]d[8] = y[8] ⊕ y[0]
y[7] = d[7] ⊕ d[1] ⊕ d[0]d[7] = y[7] ⊕ y[0]
y[6] = d[6] ⊕ d[1] ⊕ d[0]d[6] = y[6] ⊕ y[0]
y[5] = d[5] ⊕ d[1] ⊕ d[0]d[5] = y[5] ⊕ y[0]
y[4] = d[4] ⊕ d[1] ⊕ d[0]d[4] = y[4] ⊕ y[0]
y[3] = d[3] ⊕ d[1] ⊕ d[0]d[3] = y[3] ⊕ y[0]
y[2] = d[2] ⊕ d[1] ⊕ d[0]d[2] = y[2] ⊕ y[0]
y[1] = d[1]d[1] = y[1]
y[0] = d[0] ⊕ d[1]d[0] = y[0] ⊕ y[1]
strobe_y = strobe ⊕ d[1] ⊕ d[0]strobe = strobe_y ⊕ y[0]
Table 7-13 Scrambling and Descrambling Operations (11-Bit Mode, LWIDTH = 0x1)
SCRAMBLERDESCRAMBLER
y[11] = d[11] ⊕ d[2] ⊕ d[1]d[11] = y[11] ⊕ y[1]
y[10] = d[10] ⊕ d[2] ⊕ d[1]d[10] = y[10] ⊕ y[1]
y[9] = d[9] ⊕ d[2] ⊕ d[1]d[9] = y[9] ⊕ y[1]
y[8] = d[8] ⊕ d[2] ⊕ d[1]d[8] = y[8] ⊕ y[1]
y[7] = d[7] ⊕ d[2] ⊕ d[1]d[7] = y[7] ⊕ y[1]
y[6] = d[6] ⊕ d[2] ⊕ d[1]d[6] = y[6] ⊕ y[1]
y[5] = d[5] ⊕ d[2] ⊕ d[1]d[5] = y[5] ⊕ y[1]
y[4] = d[4] ⊕ d[2] ⊕ d[1]d[4] = y[4] ⊕ y[1]
y[3] = d[3] ⊕ d[2] ⊕ d[1]d[3] = y[3] ⊕ y[1]
y[2] = d[2]d[2] = y[2]
y[1] = d[2] ⊕ d[1]d[1] = y[2] ⊕ y[1]
y[0] = d[2] ⊕ d[1] ⊕ d[0](1)d[0] = y[1] ⊕ y[0](1)
strobe_y = strobe ⊕ d[1] ⊕ d[0]strobe = strobe_y ⊕ y[1]
(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.
Table 7-14 Scrambling and Descrambling Operations (10-Bit Mode, LWIDTH = 0x2)
SCRAMBLERDESCRAMBLER
y[11] = d[11] ⊕ d[3] ⊕ d[2]d[11] = y[11] ⊕ y[2]
y[10] = d[10] ⊕ d[3] ⊕ d[2]d[10] = y[10] ⊕ y[2]
y[9] = d[9] ⊕ d[3] ⊕ d[2]d[9] = y[9] ⊕ y[2]
y[8] = d[8] ⊕ d[3] ⊕ d[2]d[8] = y[8] ⊕ y[2]
y[7] = d[7] ⊕ d[3] ⊕ d[2]d[7] = y[7] ⊕ y[2]
y[6] = d[6] ⊕ d[3] ⊕ d[2]d[6] = y[6] ⊕ y[2]
y[5] = d[5] ⊕ d[3] ⊕ d[2]d[5] = y[5] ⊕ y[2]
y[4] = d[4] ⊕ d[3] ⊕ d[2]d[4] = y[4] ⊕ y[2]
y[3] = d[3]d[3] = y[3]
y[2] = d[2] ⊕ d[3]d[2] = y[2] ⊕ y[3]
y[1] = 0 (not used)d[1] = 0 (not used)
y[0] = d[0] ⊕ d[3] ⊕ d[2](1)d[0] = y[0] ⊕ y[2](1)
strobe_y = strobe ⊕ d[3] ⊕ d[2]strobe = strobe_y ⊕ y[2]
(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.
Table 7-15 Scrambling and Descrambling Operations (8-Bit Mode, LWIDTH = 0x3)
SCRAMBLERDESCRAMBLER
y[11] = d[11] ⊕ d[5] ⊕ d[4]d[11] = y[11] ⊕ y[4]
y[10] = d[10] ⊕ d[5] ⊕ d[4]d[10] = y[10] ⊕ y[4]
y[9] = d[9] ⊕ d[5] ⊕ d[4]d[9] = y[9] ⊕ y[4]
y[8] = d[8] ⊕ d[5] ⊕ d[4]d[8] = y[8] ⊕ y[4]
y[7] = d[7] ⊕ d[5] ⊕ d[4]d[7] = y[7] ⊕ y[4]
y[6] = d[6] ⊕ d[5] ⊕ d[4]d[6] = y[6] ⊕ y[4]
y[5] = d[5]d[5] = y[5]
y[4] = d[4] ⊕ d[5]d[4] = y[4] ⊕ y[5]
y[3] = 0 (not used)d[3] = 0 (not used)
y[2] = 0 (not used)d[2] = 0 (not used)
y[1] = 0 (not used)d[1] = 0 (not used)
y[0] = d[0] ⊕ d[5] ⊕ d[4](1)d[0] = y[0] ⊕ y[4](1)
strobe_y = strobe ⊕ d[5] ⊕ d[4]strobe = strobe_y ⊕ y[4]
(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.