JAJSFG3C
may 2018 – may 2023
ADC12DL3200
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: DC Specifications
6.6
Electrical Characteristics: Power Consumption
6.7
Electrical Characteristics: AC Specifications (Dual-Channel Mode)
6.8
Electrical Characteristics: AC Specifications (Single-Channel Mode)
6.9
Timing Requirements
6.10
Switching Characteristics
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Inputs
7.3.1.1
Analog Input Protection
7.3.1.2
Full-Scale Voltage (VFS) Adjustment
7.3.1.3
Analog Input Offset Adjust
7.3.2
ADC Core
7.3.2.1
ADC Theory of Operation
7.3.2.2
ADC Core Calibration
7.3.2.3
ADC Overrange Detection
7.3.2.4
Code Error Rate (CER)
7.3.2.5
Internal Dither
7.3.3
Timestamp
7.3.4
Clocking
7.3.4.1
Noiseless Aperture Delay Adjustment (tAD Adjust)
7.3.4.2
Aperture Delay Ramp Control (TAD_RAMP)
7.3.4.3
SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
7.3.4.3.1
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
7.3.4.3.2
Automatic SYSREF Calibration
7.3.5
LVDS Digital Interface
7.3.5.1
Multi-Device Synchronization and Deterministic Latency Using Strobes
7.3.5.1.1
Dedicated Strobe Pins
7.3.5.1.2
Reduced Width Interface With Dedicated Strobe Pins
7.3.5.1.3
LSB Replacement With a Strobe
7.3.5.1.4
Strobe Over All Data Pairs
7.3.6
Alarm Monitoring
7.3.6.1
Clock Upset Detection
7.3.7
Temperature Monitoring Diode
7.3.8
Analog Reference Voltage
7.4
Device Functional Modes
7.4.1
Dual-Channel Mode (Non-DES Mode)
7.4.2
Internal Dither Modes
7.4.3
Single-Channel Mode (DES Mode)
7.4.4
LVDS Output Driver Modes
7.4.5
LVDS Output Modes
7.4.5.1
Staggered Output Mode
7.4.5.2
Aligned Output Mode
7.4.5.3
Reducing the Number of Strobes
7.4.5.4
Reducing the Number of Data Clocks
7.4.5.5
Scrambling
7.4.5.6
Digital Interface Test Patterns and LVSD SYNC Functionality
7.4.5.6.1
Active Pattern
7.4.5.6.2
Synchronization Pattern
7.4.5.6.3
User-Defined Test Pattern
7.4.6
Power-Down Modes
7.4.7
Calibration Modes and Trimming
7.4.7.1
Foreground Calibration Mode
7.4.7.2
Background Calibration Mode
7.4.7.3
Low-Power Background Calibration (LPBG) Mode
7.4.8
Offset Calibration
7.4.9
Trimming
7.5
Programming
7.5.1
Using the Serial Interface
7.5.1.1
SCS
7.5.1.2
SCLK
7.5.1.3
SDI
7.5.1.4
SDO
7.5.1.5
78
7.5.1.6
Streaming Mode
7.5.1.7
80
7.6
Register Maps
7.6.1
SPI_REGISTER_MAP Registers
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Wideband RF Sampling Receiver
8.2.1.1
Design Requirements
8.2.1.1.1
Input Signal Path
8.2.1.1.2
Clocking
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Calculating Values of AC-Coupling Capacitors
8.2.1.3
Application Curves
8.2.2
Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
8.2.2.1
Design Requirements
8.2.2.1.1
Input Signal Path
8.2.2.1.2
Clocking
8.2.2.1.3
The ADC12DL3200
8.2.2.2
Application Curves
8.3
Initialization Set Up
8.4
Power Supply Recommendations
8.4.1
Power Sequencing
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.2
ドキュメントの更新通知を受け取る方法
8.3
サポート・リソース
8.4
商標
8.5
静電気放電に関する注意事項
8.6
用語集
9
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ACF|256
MPBGAO1C
ALJ|256
MPBGAS8B
サーマルパッド・メカニカル・データ
発注情報
jajsfg3c_oa
jajsfg3c_pm
8.2.2.1
Design Requirements