JAJSF36L November   2008  – February 2019 ADC14155QML-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions and Equivalent Circuits
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  ADC14155 Converter Electrical Characteristics DC Parameters
    6. 6.6  ADC14155 Converter Electrical Characteristics (Continued) DYNAMIC Parameters
    7. 6.7  ADC14155 Converter Electrical Characteristics (Continued) Logic and Power Supply Electrical Characteristics
    8. 6.8  ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics
    9. 6.9  Timing Diagram
    10. 6.10 Transfer Characteristic
    11. 6.11 Typical Performance Characteristics, DNL, INL
    12. 6.12 Typical Performance Characteristics, Dynamic Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Differential Analog Input Pins
        2. 7.3.1.2 Driving The Analog Inputs
        3. 7.3.1.3 Input Common Mode Voltage
      2. 7.3.2 Reference Pins
      3. 7.3.3 Digital Inputs
        1. 7.3.3.1 Clock Inputs
        2. 7.3.3.2 Power-Down (PD)
        3. 7.3.3.3 Clock Mode Select/Data Format (CLK_SEL/DF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Radiation Environments
      1. 8.3.1 Total Ionizing Dose (TID)
      2. 8.3.2 Single Event Effects
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NBA|48
サーマルパッド・メカニカル・データ
発注情報

6.8 ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics(11)

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V, Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset Binary Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C(1)(4)(5)(2)
PARAMETER TEST CONDITIONS NOTES TYP(6) MIN MAX UNITS SUB-GROUPS
Maximum clock frequency 155 MHz
Minimum clock frequency 5 MHz
Clock high time 3.0 ns
Clock low time 3.0 ns
Conversion latency See(13) 8 Clock cycles
tOD Output delay of CLK to DATA Relative to falling edge of CLK 2.0 ns
tSU Data output setup time Relative to DRDY See(12) 2.1 1.22 ns
tH Data output hold time Relative to DRDY See(12) 2.1 1.83 ns
tAD Aperture delay 0.5 ns
tAJ Aperture jitter 0.08 ps rms
Power down recovery time 0.1 µF to GND on pins 43, 44; 10 µF and 0.1 µF between pins 43, 44; 0.1 µF and 10 µF to GND on pins 47, 48 3.0 ms
(1) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0 V, unless otherwise specified.
(2) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.
(3) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described in the Recommended Operating Conditions section.

ADC14155QML-SP 20210711.gif
(4) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(5) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
(6) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured.
(7) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale.
(8) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
(9) Optimum performance will be obtained by keeping the reference input in the 0.9-V to 1.1-V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for external reference applications.
(10) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR(C0 × f0 + C1 × f1 +....C11 × f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
(11) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-STD-883, Test Method 1019.
(12) Specified by characterization.
(13) Specified by design.